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PDF DS1100L Data sheet ( Hoja de datos )
| Número de pieza | DS1100L | |
| Descripción | 3.3V 5-Tap Economy Timing Element Delay Line | |
| Fabricantes | Dallas Semiconductor | |
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PRELIMINARY
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FEATURES
§ All-Silicon Timing Circuit
§ Five Taps Equally Spaced
§ Delays are Stable and Precise
§ Both Leading- and Trailing-Edge Accuracy
§ 3.3V Version of the DS1100
§ Low-Power CMOS
§ TTL-/CMOS-compatible
§ Vapor-Phase and IR Solderable
§ Custom Delays Available
§ Fast-Turn Prototypes
§ Delays Specified Over Both Commercial and
Industrial Temperature Ranges
DS1100L
3.3V 5-Tap Economy Timing
Element (Delay Line)
PIN ASSIGNMENT
IN
TAP 2
TAP 4
GND
1
2
3
4
8 VCC
7 TAP 1
6 TAP 3
5 TAP 5
DS1100LZ SO (150mil)
DS1100LU µSOP
PIN DESCRIPTION
TAP 1 to TAP 5 - TAP Output Number
VCC
GND
- +3.3V
- Ground
IN - Input
DESCRIPTION
The DS1100L is a 3.3V version of the DS1100. It is characterized for operation over the range 3.0V to
3.6V. The DS1100L series delay lines have five equally spaced taps providing delays from 4ns to 500ns.
These devices are offered in surface-mount packages to save PC board area. Low cost and superior
reliability over hybrid technology is achieved by the combination of a 100% silicon delay line and
industry-standard µSOP and SO packaging. The DS1100L 5-tap silicon delay line reproduces the input-
logic state at the output after a fixed delay as specified by the extension of the part number after the dash.
The DS1100L is designed to reproduce both leading and trailing edges with equal precision. Each tap is
capable of driving up to ten 74LS loads.
Dallas Semiconductor can customize standard products to meet special needs.
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DS1100L
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of any tap output pulse.
tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on the trailing edge of any tap output pulse.
TEST SETUP DESCRIPTION
Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the
DS1100L. The input waveform is produced by a precision pulse generator under software control. Time
delays are measured by a time interval counter (20ps resolution) connected between the input and each
tap. Each tap is selected and connected to the counter by a VHF switch control unit. All measurements
are fully automated, with each instrument controlled by a central computer over an IEEE 488 bus.
TEST CONDITIONS INPUT:
Ambient Temperature: 25°C ±3°C
Supply Voltage (VCC): 3.3V ±0.1V
Input Pulse:
High = 3.0V ± 0.1V
Low = 0.0V ± 0.1V
Source Impedance:
50W max
Rise and Fall Time:
3.0ns max (measured between 10% and 90%)
Pulse Width:
500ns (1µs for -500 version)
Period:
1µs (2µs for -500 version)
OUTPUT:
Each output is loaded with the equivalent of one 74F04 input gate. Delay is measured at the 1.5V level on
the rising and falling edge.
NOTE:
Above conditions are for test only and do not restrict the operation of the device under other data sheet
conditions.
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5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet DS1100L.PDF ] | |
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