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PDF U630H16XS Data sheet ( Hoja de datos )
| Número de pieza | U630H16XS | |
| Descripción | HardStore 2K x 8 nvSRAM Die | |
| Fabricantes | Simtek Corporation | |
| Logotipo |  |
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Obsolete - Not Recommended for New Designs
U630H16XS
HardStore 2K x 8 nvSRAM Die
Features
Description
• High-performance CMOS non-
volatile static RAM 2048 x 8 bits
• 25, 35 and 45 ns Access Times
• 12, 20 and 25 ns Output Enable
Access Times
• Hardware STORE Initiation
(STORE Cycle Time < 10 ms)
• Automatic STORE Timing
• 106 STORE cycles to EEPROM
• 100 years data retention in
EEPROM
• Automatic RECALL on Power Up
• Hardware RECALL Initiation
(RECALL Cycle Time < 20 μs)
• Unlimited RECALL cycles from
EEPROM
• Unlimited SRAM Read and Write
• Single 5 V ± 10 % Operation
• Operating temperature ranges:
0 to 70 °C
-40 to 85 °C
• QS 90000 Quality Standard
• ESD protection > 2000 V
(MIL STD 883C M3015.7-HBM)
The U630H16 has two separate
modes of operation: SRAM mode
and non-volatile mode, determined
by the state of the NE pad.
In SRAM mode, the memory ope-
rates as an ordinary static RAM. In
non-volatile operation, data is
transferred in parallel from SRAM
to EEPROM or from EEPROM to
SRAM. In this mode SRAM
functions are disabled.
The U630H16 is a fast static RAM
(25, 35, 45 ns), with a non-volatile
electrically erasable PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent non-volatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation), or from the
EEPROM to the SRAM (the
RECALL operation) are initiated
through the state of the NE pad.
The U630H16 combines the high
performance and ease of use of a
fast SRAM with non-volatile data
integrity.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the non-vola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The non-volatile data can be
recalled an unlimited number of
times.
The chips are tested with a
restricted wafer probe program
at room temperature only. Unte-
sted parameters are marked with
a number sign (#).
Pad Configuration
Pad Description
A5 A6 A7 NE VCC
VBND
W HSB A8 A9
A4 W
A3 G
A2 A10
A1 E
A0 DQ0 DQ1 DQ2 VSS VCC DQ3 DQ4 DQ5 DQ6 DQ7
Signal Name
A0 - A10
DQ0 - DQ7
E
G
W
NE
VCC
VSS
VBND
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Nonvolatile Enable
Power Supply Voltage
Ground
HardStore type enable
March 31, 2006
STK Control #ML0039
1
Rev 1.0
1 page  
U630H16XS
Read Cycle 1: Ai-controlled (during Read cycle: E = G = VIL, W = NE = VIH)f
Ai
DQi
Output
tcR (1)
Address Valid
ta(A) (2)
Previous Data Valid
tv(A) (9)
Output Data Valid
Read Cycle 2: G-, E-controlled (during Read cycle: W = NE = VIH)g
Ai
E
G
DQi
Output
ICC
tcR (1)
Address Valid
ta(A) (2)
ta(E) (3)
ten(E) (7)
ta(G) (4)
ten(G) (8)
High Impedance
ACTIVE
tPU (10)
STANDBY
tdis(E)
(5)
tdis(G) (6)
Output Data Valid
tPD (11)
No.
Switching Characteristics
Write Cycle
12 Write Cycle Time
13 Write Pulse Width
14 Write Pulse Width Setup Time
15 Address Setup Time
16 Address Valid to End of Write
17 Chip Enable Setup Time
18 Chip Enable to End of Write
19 Data Setup Time to End of Write
20 Data Hold Time after End of Write
21 Address Hold after End of Write
22 W LOW to Output in High-Zh, i
23 W HIGH to Output in Low-Z
Symbol
Alt. #1 Alt. #2 IEC
25 35 45
Unit
Min. Max. Min. Max. Min. Max.
tAVAV tAVAV
tcW 25#
35#
45#
tWLWH
tw(W) 20# 30# 35#
tWLEH tsu(W) 20# 30# 35#
tAVWL tAVEL tsu(A) 0# 0# 0#
tAVWH tAVEH tsu(A-WH) 20#
30#
35#
tELWH
tsu(E) 20# 30# 35#
tELEH tw(E) 20# 30 35#
tDVWH tDVEH tsu(D) 12# 18 20#
tWHDX tEHDX
th(D)
0#
0#
0#
tWHAX tEHAX
th(A)
0#
0#
0#
tWLQZ
tdis(W) 10# 13# 15#
tWHQX
ten(W) 5# 5# 5#
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
March 31, 2006
STK Control #ML0039
5
Rev 1.0
5 Page 
Test Configuration for Functional Check
U630H16XS
VCCt
5V
A0
A1
A2 DQ0
A3 DQ1
480
VIH
A4
A5
DQ2
A6 DQ3
A7 DQ4
A8 DQ5
VIL
A9
A10
DQ6
DQ7
VO
NE
E
W
G VSS
30 pF s
255
s: In measurement of tdis-times and ten-times the capacitance is 5 pF.
t: Between VCC and VSS must be connected a high frequency bypass capacitor 0.1 μF to avoid disturbances.
Capacitancee
Conditions
Symbol
Min.
Max.
Input Capacitance
Output Capacitance
VCC = 5.0 V
VI = VSS
f = 1 MHz
Ta = 25 °C
CI
CO
All pads not under test must be connected with ground by capacitors.
8
7
Ordering Code
Example
Type
bare die
U630H16 XS C 25
Operating Temperature Range
C = 0 to 70 °C
K = -40 to 85 °C
A = -40 to 125 °C (only 35 ns)
Access Time
25 = 25 ns
35 = 35 ns
45 = 45 ns
Unit
pF
pF
Bonding Instructions
The U630H16XS has 30 relevant bond pads and 4 additional pads.
The 4 additional pads must not be bonded.
Refer to the bond pad location and identification table for a complete list of bond pads and coordinates.
It is mandatory to use a bond wire on each VCC and two bond wires on VSS bond pad for noise immunity.
The backside of the die is connected to VCC and can be contacted with the substrate in case of the same potential.
The pad VBND has to be connected with VCC in order to enable the HardStore mode of the chip.
March 31, 2006
STK Control #ML0039
11
Rev 1.0
11 Page | ||
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| PDF Descargar | [ Datasheet U630H16XS.PDF ] | |
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