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PDF N32T1630C1C Data sheet ( Hoja de datos )
| Número de pieza | N32T1630C1C | |
| Descripción | 32Mb Ultra-Low Power Asynchronous CMOS Pseudo SRAM | |
| Fabricantes | NanoAmp Solutions | |
| Logotipo |  |
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www.DataSheet4U.com
NanoAmp Solutions, Inc.
670 North McCarthy Blvd. Suite 220, Milpitas, CA 95035
ph: 408-935-7777, FAX: 408-935-7770
www.nanoamp.com
N32T1630C1C
32Mb Ultra-Low Power Asynchronous CMOS Pseudo SRAM
w/ Page Mode Operation (2M x 16 bit)
Overview
Features
The N32T1630C1C is an integrated memory
device containing a 32 Mbit SRAM built using a
self-refresh DRAM array organized as 2,097,152
words by 16 bits. The device is designed and
fabricated using NanoAmp’s advanced CMOS
technology to provide both high-speed
performance and ultra-low power. It is designed to
be identical in operation and interface to standard
6T SRAMS. Byte controls (UB and LB) allow the
upper and lower bytes to be accessed
independently and can also be used to deselect
the device. The N32T1630C1C offers a very high
speed page mode operation for improved
performance and operating power savings. The
device is optimal for various applications where
low-power is critical such as battery backup and
hand-held devices. Also included are several
power savings modes: a deep sleep mode and
partial array refresh mode where data is retained in
a portion of the array. The device can operate over
a very wide temperature range of -25oC to +85oC
and is available in a JEDEC standard VFRBGA
package compatible with other standard 2Mb x 16
SRAMs.
• Dual voltage for Optimum Performance:
VccQ - 2.7 to 3.6 Volts
Vcc - 2.7 to 3.6 Volts (Vcc ≤ VccQ)
• Fast random access time
70ns at 2.7V
• Very fast page mode access time
25ns page cycle and access
• Very low standby current
80µA V (Typical)
• Very low operating current
1.0mA at 1µs (Typical)
• Simple memory control
Byte control for independent byte operation
Output Enable (OE) for memory expansion
• Automatic power down to standby mode
• PAR and RMS power saving modes
• Deep sleep option
• TTL compatible three-state output driver
Product Family
Part Number
Package
Type
Operating
Temperature
N32T1630C1CZ 48-VFRBGA -25oC to +85oC
Power
Supply
2.7V - 3.6V (VCC)
Speed
Standby
Operating
Current (ISB), Current (Icc),
Max Max
70ns 135 µA @ 3.3V 3 mA @ 1MHz
Pin Configuration (Top View)
Pin Descriptions
123456
A LB OE A0
B I/O8 UB A3
C I/O9 I/O10 A5
A1 A2 ZZ
A4 CE I/O0
A6 I/O1 I/O2
D VSSQ I/O11 A17 A7 I/O3 VCC
E VCCQ
I/O12
DNU/
VSS
A16
I/O4
VSS
F I/O14 I/O13 A14 A15 I/O5 I/O6
G I/O15 A19 A12 A13 WE I/O7
H A18 A8
A9 A10 A11 A20
48 Ball VFRBGA
6 x 8 mm
Pin Name
A0-A20
WE
CE
OE
UB,LB
ZZ
I/O0-I/O15
VCC
VCCQ
VSS
VSSQ
DNU
Pin Function
Address Inputs
Write Enable Input
Chip Enable Input
Output Enable Input
Byte Enable Inputs
Deep Sleep Input
Data Inputs/Outputs
Core Power
I/O Power
Ground
I/O Ground
Do Not Use
(DOC# 14-02-005 Rev C ECN 01-0918)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
1
1 page  
NanoAmp Solutions, Inc.
Timing
Item
Read Cycle Time
Address Access Time
Page Mode Read Cycle Time
Page Mode Access Time
Chip Enable to Valid Output
Output Enable to Valid Output
Byte Select to Valid Output
Chip Enable to Low-Z output
Output Enable to Low-Z Output
Byte Select to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Byte Select Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
Page Mode Write Cycle Time
Chip Enable to End of Write
Address Valid to End of Write
Byte Select to End of Write
Write Pulse Width
Address Setup Time
Write Recovery Time
Write to High-Z Output
Data to Write Time Overlap
Page Mode Data to Write Time Overlap
Data Hold from Write Time
Page Mode Data Hold from Write Time
End Write to Low-Z Output
CE Precharge
Maximum Page Mode Cycle
N32T1630C1C
Symbol
tRC
tAA
tPC
tPA
tCO
tOE
tLB, tUB
tLZ
tOLZ
tLBZ, tUBZ
tHZ
tOHZ
tLBHZ, tUBHZ
tOH
tWC
tPWC
tCW
tAW
tLBW, tUBW
tWP
tAS
tWR
tWHZ
tDW
tPDW
tDH
tPDH
tOW
tCP
tPGMAX
70ns
Min.
Max.
70
70
25 20000
25
70
20
70
10
5
10
0 20
0 20
0 20
5
70
25 20000
60
60
60
55 20000
0
0
20
25
20
0
0
5
10
20000
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(DOC# 14-02-005 Rev C ECN 01-0918)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
5
5 Page 
NanoAmp Solutions, Inc.
FIGURE 2: Variable Address Register
A20 - A5
A4
A3
N32T1630C1C
A2 A1 A0
Reserved for future
Preferably set to all 0
Array mode for ZZ
0 = PAR mode (default)
1 = RMS mode
ZZ Enable/Disable
1
1
0
0
0=Deep Sleep Enabled
(default for DSA device)
1 = Deep Sleep Disabled
(default for DSI device)
Array half
0 = Bottom array (default)
1 = Top array
Array section
1 = 1/4 array
0 = 1/2 array
1 = Reserved
0 = Full array
(default)
FIGURE 3: Variable Address Register (VAR) Update Timings
A0-A4
CE
WE tCDZZ
ZZ
LB, UB
tAS
tZZWE
tWC
tAW
tWP
tLBW, UBW
tWR
FIGURE 4: Deep Sleep Mode - Entry/Exit Timings
ZZ
CE or
LB, UB
tCDZZ
tZZMIN
tR
(DOC# 14-02-005 Rev C ECN 01-0918)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
11
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| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet N32T1630C1C.PDF ] | |
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