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PDF 25F512AN Data sheet ( Hoja de datos )
| Número de pieza | 25F512AN | |
| Descripción | AT25F512AN | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0 (0,0) and 3 (1,1)
– Datasheet Describes 0 Operation
• 33 MHz Clock Rate
• Byte Mode and 128-byte Page Mode for Program Operations
• Sector Architecture:
– Two Sectors with 32K Bytes Each
– 256 Pages per Sector
• Product Identification Mode
• Low-voltage Operation
– 2.7 (VCC = 2.7 to 3.6V)
• Sector Write Protection
• Write Protect (WP) Pin and Write Disable Instructions for both Hardware and Software
Data Protection
• Self-timed Program Cycle (75 µs/byte typical)
• Self-timed Sector Erase Cycle (1 second/sector typical)
• Single Cycle Reprogramming (Erase and Program) for Status Register
• High Reliability
– Endurance: 10,000 Write Cycles Typical
– Data Retention: 20 Years
• 8-lead JEDEC SOIC and 8-lead SAP Packages
Description
The AT25F512A provides 524,288 bits of serial reprogrammable Flash memory orga-
nized as 65,536 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage operation
are essential. The AT25F512A is available in a space-saving 8-lead JEDEC SOIC and
8-lead SAP packages.
The AT25F512A is enabled through the Chip Select pin (CS) and accessed via a
three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All write cycles are completely self-timed.
Block write protection for the entire memory array is enabled by programming the sta-
tus register. Separate write enable and write disable instructions are provided for
additional data protection. Hardware data protection is provided via the Write Protect
(WP) pin to protect against inadvertent write attempts to the status register. The HOLD
pin may be used to suspend any serial communication without resetting the serial
sequence.
Table 1. Pin Configuration
Pin Name Function
CS Chip Select
SCK
Serial Data Clock
SI Serial Data Input
SO Serial Data Output
GND
Ground
VCC
Power Supply
WP Write Protect
HOLD
Suspends Serial Input
8-lead SOIC
CS
SO
WP
GND
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
8-lead SAP
VCC 8
HOLD 7
SCK 6
SI 5
1 CS
2 SO
3 WP
4 GND
Bottom View
512Kbit High
Speed SPI
Serial Flash
Memory
512K (65,536 x 8)
AT25F512A
Rev. 3345F–FLASH–11/06
1
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Serial Interface
Description
AT25F512A
MASTER: The device that generates the serial clock.
SLAVE: Because the SCK pin is always an input, the AT25F512A always operates as a
slave.
TRANSMITTER/RECEIVER: The AT25F512A has separate pins designated for data
transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be
received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25F512A, and the serial output pin (SO) will remain in a high impedance state until
the falling edge of CS is detected again. This will reinitialize the serial communication.
CHIP SELECT: The AT25F512A is selected when the CS pin is low. When the device is
not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will
remain in a high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25F512A.
When the device is selected and a serial sequence is underway, HOLD can be used to
pause the serial communication with the master device without resetting the serial
sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To
resume serial communication, the HOLD pin is brought high while the SCK pin is low
(SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin
is in the high impedance state.
WRITE PROTECT: The AT25F512A has a write lockout feature that can be activated by
asserting the WP pin. When the lockout feature is activated, locked-out sectors will be
read only. The write protect pin will allow normal read/write operations when held high.
When the WP is brought low and WPEN bit is “1”, all write operations to the status register
are inhibited. WP going low while CS is still low will interrupt a write to the status register.
If the internal status register write cycle has already been initiated, WP going low will have
no effect on any write operation to the status register. The WP pin function is blocked
when the WPEN bit in the status register is “0”. This will allow the user to install the
AT25F512A in a system with the WP pin tied to ground and still be able to write to the sta-
tus register. All WP pin functions are enabled when the WPEN bit is set to “1”.
3345F–FLASH–11/06
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Timing Diagrams (for SPI Mode 0 (0, 0))
Figure 3. Synchronous Data Timing
VIH
CS
VIL
tCSS
SCK
VIH
VIL
VIH
SI
VIL
tWH
tSU
VALID IN
tH
VOH
SO
VOL
HI-Z
Figure 4. WREN Timing
CS
tWL
tV
SCK
SI
WREN OP-CODE
SO
Figure 5. WRDI Timing
CS
HI-Z
SCK
SI WRDI OP-CODE
SO HI-Z
AT25F512A
tCS
tCSH
tHO tDIS
HI-Z
3345F–FLASH–11/06
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet 25F512AN.PDF ] | |
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