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PDF GSCNE555 Data sheet ( Hoja de datos )
| Número de pieza | GSCNE555 | |
| Descripción | SINGLE TIMER | |
| Fabricantes | GTM | |
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GSCNE555
SINGLE TIMER
ISSUED DATE :2005/08/10
REVISED DATE :2006/05/15C
Description
The GSCNE555 is a highly stable timer integrated circuit. It can be operated in Astable mode and Monostable
mode. With monostable operation, the time delay is controlled by one external and one capacitor. With a stable
operation, the frequency and duty cycle are accurately controlled with two external resistors and one capacitor.
Features
High current driver capability (=200mA)
Adjustable duty cycle
Timing form Sec to Hours
Turn off time less than 2 Sec
Applications
Precision timing
Pulse generation
Time delay generation
Package Dimensions
REF.
A
B
C
D
E
F
Millimeter
Min. Max.
5.80
6.20
4.80
5.00
3.80
4.00
0° 8°
0.40
0.90
0.19
0.25
Block Diagram and Simplified Application & Pin Configuration
REF.
M
H
L
J
K
G
Millimeter
Min. Max.
0.10
0.25
0.35
0.49
1.35
1.75
0.375 REF.
45°
1.27 TYP.
GSCNE555
Page: 1/5
1 page  
Application Circuit
ISSUED DATE :2005/08/10
REVISED DATE :2006/05/15C
GSCNE555
FLIP-FLOP
Application Notes
The application circuit shows astable mode configuration.
Pin 6 (Threshold) is tied to Pin 2 (Trigger) and Pin 4 (Reset) is tied to VCC (Pin 8). The external capacitor C1
of Pin 6 and Pin 2 charges through RA, RB and discharge through RB only. In the internal circuit of
GSCNE555, one input of the upper comparator is at voltage of 2/3VCC (R1=R2=R3), another input is
connected to Pin 6. As soon as C1 is charging to higher than 2/3VCC, transistor Q1 is turned ON and
discharge C1 to collector voltage of transistor Q1. Therefore, the flip-flop circuit is reset and output is low. One
input of lower comparator is at voltage of 1/3VCC, discharge transistor Q1 turn off and C1 charges through RA
and RB. Therefore, flip-flop circuit is set output high.
That is, when C1 charges through RA and RB, output is high and when C1 discharge through RB, output is
low. The charge time (output is high) t1 is 0.693 (RA+RB) C1 and the discharge time (output is low) T2 is
0.693RB*C1.
In
Vcc-
1
3
Vcc
Vcc-
2
13
Vcc
=0.693
Thus the total period time T is given by
T1=0.693*(RA+RB)*C1
T2=0.693*RB*C1
T=T1+T2=0.693(RA+2RB)*C1
Then the frequency of astable mode is given by
f=
1
T
=
1.44
(RA+2RB)*C1
The duty cycle is given by
D.C.
=
T2
T
=
RB
RA+2RB
Important Notice:
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written approval of GTM.
GTM reserves the right to make changes to its products without notice.
GTM semiconductor products are not warranted to be suitable for use in life-support Applications, or systems.
GTM assumes no liability for any consequence of customer product design, infringement of patents, or application assistance.
Head Office And Factory:
Taiwan: No. 17-1 Tatung Rd. Fu Kou Hsin-Chu Industrial Park, Hsin-Chu, Taiwan, R. O. C.
TEL : 886-3-597-7061 FAX : 886-3-597-9220, 597-0785
China: (201203) No.255, Jang-Jiang Tsai-Lueng RD. , Pu-Dung-Hsin District, Shang-Hai City, China
TEL : 86-21-5895-7671 ~ 4 FAX : 86-21-38950165
GSCNE555
Page: 5/5
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| PDF Descargar | [ Datasheet GSCNE555.PDF ] | |
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