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PDF MAX3984 Data sheet ( Hoja de datos )
| Número de pieza | MAX3984 | |
| Descripción | 1Gbps to 10Gbps Preemphasis Driver | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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19-0868; Rev 0; 7/07
1Gbps to 10Gbps Preemphasis Driver with
Receive Equalizer
General Description
The MAX3984 is a single-channel, preemphasis driver
with input equalization that operates from 1Gbps to
10.3Gbps. It provides compensation for copper links,
such as 8.5Gbps Fibre Channel and 10.3Gbps
Ethernet, allowing spans of up to 10m with 24 AWG
cable. The driver provides four selectable preemphasis
levels, and the selectable input equalizer compensates
for up to 10in of FR-4 circuit board material at 10Gbps.
The MAX3984 also features SFP-compliant loss-of-sig-
nal (LOS) detection and TX_DISABLE. Selectable out-
put swing reduces EMI and power consumption. The
MAX3984 is packaged in a lead-free, 3mm x 3mm,
16-pin thin QFN and operates from a 0°C to +85°C tem-
perature range.
Applications
8.5Gbps Fibre Channel Active Cable Assemblies
10.3Gbps Ethernet
STM-64
Pin Configuration appears at end of data sheet.
Features
♦ Drives Up to 10m of 24 AWG Cable
♦ Drives Up to 30in of FR-4
♦ Selectable 1000mVP-P or 1200mVP-P Differential
Output Swing
♦ Selectable Output Preemphasis
♦ Selectable Input Equalization
♦ LOS Detection with Built-In Squelch
♦ Transmit Disable
♦ Hot Pluggable
Ordering Information
PART
TEMP
RANGE
PIN-PACKAGE
PKG
CODE
MAX3984UTE+ 0°C to +85°C 16 Thin QFN-EP* T1633F-3
+Denotes a lead-free package.
*EP = Exposed pad.
Typical Operating Circuits
DISK
ENCLOSURE
SWITCH
OR
SERDES
Tx+
Tx-
Rx+
Rx-
≤ 5V
≥ 4.7kΩ
+3.3V
TX_DISABLE VCC
PE0
VCC PE1
LOS
OR
GND IN_LEV MAX3984
0.01μF
OUT_LEV
IN+
OUT+
0.01μF
IN-
GND OUT-
0.01μF
OUT+
+3.3V
0.01μF
OUT-
PE0
VCC PE1 MAX3984
OR
GND IN_LEV
OUT_LEV
LOS GND
IN+
IN-
ACTIVE CABLE ASSEMBLY
≤ 10m (24 AWG)
UP TO 10Gbps
COPPER CABLE
DIFFERENTIAL
100Ω TWIN-AX
0.01μF
39Ω
22pF
39Ω
22pF 0.01μF
0.01μF
22pF
39Ω
22pF 0.01μF
39Ω
FABRIC SWTCH
≤ 5V
+3.3V
LOS
PE0
PE1
MAX3984 IN_LEV
VCC
OR
GND
OUT_LEV
0.01μF
IN+ OUT+
IN- GND OUT-
0.01μF
RPULLUP
≥ 4.7kΩ
SWITCH
OR
SERDES
Rx+
Rx-
+3.3V
OUT+ VCC
0.01μF
IN+
OUT- IN-
PE0 0.01μF
LOS MAX3984 PE1
IN_LEV
VCC
OR
GND
OUT_LEV
GND TX_DISALBOLSE
Tx+
Tx-
Typical Operating Circuits continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1 page  
1Gbps to 10Gbps Preemphasis Driver with
Receive Equalizer
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = 0°C to +85°C. Typical values are at TA = +25°C, VCC = +3.3V, unless otherwise noted.)
PARAMETER
LOS Open-Collector Current
Sink
LOS Response Time
(Note 4)
SYMBOL
CONDITIONS
LOS asserted
LOS asserted; VOL 0.4V
(Note 12)
Time from VIN dropping below deassert level
or rising above assert level to 50% point of
LOS output transition
MIN
0
1.0
0
TYP
MAX
25
25
UNITS
μA
mA
μA
10 μs
LOS Transition Time
Rise time or fall time (10% to 90%);
pullup supply = 5.5V; external pullup
R 4.7k
200 ns
CONTROL INPUTS: TX_DISABLE, PE0, PE1, OUT_LEV, IN_LEV
Logic-High Voltage
Logic-Low Voltage
Logic-High Current
Logic-Low Current
VIH
VIL
IIH
Current required to maintain logic-high state
at VIH > +2.0V
IIL
Current required to maintain logic-low state
at VIL < +0.8V
2.0
0.8
-150
350
V
V
μA
μA
Note 1: Supply voltage to reach 90% of final value in less than 100µs, but not less than 10µs. Power-on delay interval measured
from the 50% level of the final voltage at the filter’s device side to 50% level of final current. The supply is to remain at or
above 3V for at least 100ms. Only one full-scale transition is permitted during this interval. Aberrations on the transition are
limited to less than 100mV.
Note 2: IN+ and IN- are single-ended, 50Ω terminations to (VCC - 1.5V) ±0.2V.
Note 3: Load is 50Ω ±1% at each side and the pattern is 0000011111 or equivalent pattern at 2.5Gbps.
Note 4: Guaranteed by design and characterization.
Note 5: PE1 = PE0 = logic-high (maximum preemphasis), load is 50Ω ±1% at each side. The pattern is 11001100 (50% edge den-
sity) at 10Gbps. AC common-mode output is computed as:
where:
VACCM_RMS = RMS[(VP + VN) / 2) - VDCCM]
Note 6:
VP = time-domain voltage measured at OUT+ with at least 10GHz bandwidth.
VN = time-domain voltage measured at OUT- with at least 10GHz bandwidth.
AC common-mode voltage (VACCM_RMS) expressed as an RMS value.
DC common-mode voltage (VDCCM) = average DC voltage of (VP + VN) / 2.
Using 0000011111 or equivalent pattern at 2.5Gbps. PE0 = PE1 = logic-low for minimum preemphasis. Measured within
2in of the output pins with Rogers 4350 dielectric, or equivalent, and ≥ 10-mil line width. For transition time, the 0% refer-
ence is the steady state level after four zeros, just before the transition, and the 100% reference level is the steady state
level after four consecutive logic ones.
Note 7: Pattern is 0000011111 or equivalent pattern at 10Gbps and 100mVP-P differential swing. IN_LEV = logic-low and PE0 =
PE1 = logic-low for minimum preemphasis. Signal transition time is controlled by the 4th-order BT filter (7.5GHz band-
width) or equivalent. See Figure 3 for setup.
Note 8: Test pattern (464 bits): 100 zeros, 1010, PRBS7, 100 ones, 0101, PRBS7.
Note 9: Input range selection is IN_LEV = logic-high for FR-4 input equalization. Cables are unequalized, Amphenol Spectra-Strip
(160-2499-997) 24 AWG or equivalent. Residual deterministic jitter is the difference between the source jitter at point A
and the load jitter point D in Figure 2. The deterministic jitter (DJ) at the output of the transmission line must be from media
induced loss and not from clock source modulation. DJ is measured at point D of Figure 2.
Note 10: Input range selection is IN_LEV = logic-low. Residual deterministic jitter is the difference between the source jitter at point
A and the load jitter point D in Figure 3. The deterministic jitter (DJ) at the output of the transmission line must be from
media induced loss and not from clock source modulation. DJ is measured at point D of Figure 3.
Note 11: Measured with 101010… pattern at 10Gbps with less than 1in of FR-4 at the input.
Note 12: True open-collector outputs. VCC = 0 and the external 4.7kΩ pullup resistor is connected to +5.5V.
_______________________________________________________________________________________ 5
5 Page 
1Gbps to 10Gbps Preemphasis Driver with
Receive Equalizer
VCC2
10kΩ VCC2
2
PEO
LVTTL
PE1
IN+
CML
IN-
2
FIXED
EQUALIZER
1
0
IN_LEV
TX_DISABLE
OUT_LEV
VCC2
40kΩ
VCC2
VCC2
LVTTL
10kΩ
VCC2
VCC2
LVTTL
20kΩ
VCC2
LVTTL
MAX3984
LIMITER
PREEMPHASIS
CML
SIGNAL
DETECT
VCC2
OUT+
OUT-
LOS
Figure 4. Functional Diagram
GND
The IN_LEV pin sets the LOS assert and deassert lev-
els. When IN_LEV is LVTTL high or open, the LOS
assert threshold is 300mVP-P. When IN_LEV is LVTTL
low, the LOS assert threshold is 100mVP-P.
TX_DISABLE provides manual control for turning the
output off. The MAX3984 has a squelch function that
disables the output when there is an LOS condition. To
disable the squelch function, connect LOS to ground
(see the Squelch section).
Applications Information
Squelch
The MAX3984 can automatically detect an incoming
signal and enable or disable the data outputs. To
enable squelch, the LOS pin must be connected to a
TTL high or VCC with a pullup resistor (≥ 4.7kΩ).
Internally, TX_DISABLE and LOS are connected through
an OR-gate to control the CML outputs. The outputs are
disabled if LOS asserts. To turn off the squelch function,
LOS must be pulled to TTL low. The output can also be
disabled when TX_DISABLE is forced high.
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet MAX3984.PDF ] | |
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