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PDF AD8123 Data sheet ( Hoja de datos )
| Número de pieza | AD8123 | |
| Descripción | Triple Differential Receiver | |
| Fabricantes | Analog Devices | |
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Data Sheet
Triple Differential Receiver with
Adjustable Line Equalization
AD8123
FEATURES
Compensates cables to 300 meters for wideband video
Fast rise and fall times
4.9 ns with 2 V step at 150 meters of UTP cable
8.0 ns with 2 V step at 300 meters of UTP cable
55 dB peak gain at 100 MHz
Two frequency response gain adjustment pins
High frequency peaking adjustment (VPEAK)
Broadband flat gain adjustment (VGAIN)
Pole location adjustment pin (VPOLE)
Compensates for variations between cables
Can be optimized for either UTP or coaxial cable
DC output offset adjust (VOFFSET)
Low output offset voltage: 24 mV
Compensates both RGB and YPbPr
Two on-chip comparators with hysteresis
Can be used for common-mode sync extraction
Available in 40-lead, 6 mm × 6 mm LFCSP
APPLICATIONS
Keyboard-video-mouse (KVM)
Digital signage
RGB video over UTP cables
Professional video projection and distribution
HD video
Security video
GENERAL DESCRIPTION
The AD8123 is a triple, high speed, differential receiver and
equalizer that compensates for the transmission losses of UTP
and coaxial cables up to 300 meters in length. Various gain
stages are summed together to best approximate the inverse
frequency response of the cable. Logic circuitry inside the AD8123
controls the gain functions of the individual stages so that the
lowest noise can be achieved at short-to-medium cable lengths.
This technique optimizes its performance for low noise, short-
to-medium range applications, while at the same time provides
the high gain bandwidth required for long cable equalization
(up to 300 meters). Each channel features a high impedance
differential input that is ideal for interfacing directly with the cable.
The AD8123 has three control pins for optimal cable
compensation, as well as an output offset adjust pin. Two
voltage-controlled pins are used to compensate for different
cable lengths; the VPEAK pin controls the amount of high frequency
peaking and the VGAIN pin adjusts the broadband flat gain,
which compensates for the low frequency flat cable loss.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAM
VPEAK VPOLE VOFFSET VGAIN
AD8123
–INR
+INR
–ING
+ING
–INB
+INB
–INCMP1
+INCMP1
–INCMP2
+INCMP2
Figure 1.
OUTR
OUTG
OUTB
OUTCMP1
OUTCMP2
For added flexibility, an optional pole adjustment pin, VPOLE,
allows movement of the pole locations, allowing for the
compensation of different gauges and types of cable as well
as variations between different cables and/or equalizers. The
VOFFSET pin allows the dc voltage at the output to be adjusted,
adding flexibility for dc-coupled systems.
The AD8123 is available in a 6 mm × 6 mm, 40-lead LFCSP
and is rated to operate over the extended temperature range of
−40°C to +85°C.
UXGA RESOLUTION IMAGE
AFTER 300 METER CAT-5 CABLE
BEFORE AD8123.
UXGA RESOLUTION IMAGE
AFTER 300 METER CAT-5 CABLE
AFTER AD8123.
Figure 2. UXGA Resolution Images Before and After the AD8123
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2007–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD8123
Parameter
POWER SUPPLY
Operating Voltage Range
Positive Quiescent Supply Current
Negative Quiescent Supply Current
Supply Current Drift, ICC/IEE
Positive Power Supply Rejection Ratio
Negative Power Supply Rejection Ratio
Power Down, VIH (Minimum)
Power Down, VIL (Maximum)
Positive Supply Current, Powered Down
Negative Supply Current, Powered Down
COMPARATORS
Output Voltage Levels
Hysteresis
Propagation Delay
Rise/Fall Times
Output Resistance
OPERATING TEMPERATURE RANGE
Test Conditions/Comments
DC, referred to output
DC, referred to output
Minimum Logic 1 voltage
Maximum Logic 0 voltage
VPEAK = VGAIN = VPOLE = 0 V
VPEAK = VGAIN = VPOLE = 0 V
VOH/VOL
VHYST
tPD, LH/tPD, HL
tRISE/tFALL
Data Sheet
Min Typ
±4.5
132
126
80
−51
−63
1.1
0.8
1.1
0.7
3.33/0.043
70
17.5/10.0
9.3/9.3
0.03
−40
Max Unit
±5.5 V
mA
mA
µA/°C
dB
dB
V
V
µA
µA
V
mV
ns
ns
Ω
+85 °C
Rev. B | Page 4 of 16
5 Page 
AD8123
THEORY OF OPERATION
The AD8123 is a unity-gain, triple, wideband, low noise analog
line equalizer that compensates for losses in UTP and coaxial
cables up to 300 meters in length. The 3-channel architecture is
targeted at high resolution RGB applications but can be used in
HD YPbPr applications as well.
Three continuously adjustable control voltages, common
to the RGB channels, are available to the designer to provide
compensation for various cable lengths as well as for variations
in the cable itself. The VPEAK input is used to control the amount
of high frequency peaking. VPEAK is the primary control that is
used to compensate for frequency and cable-length dependent,
high frequency losses that are present due to the skin effect of
the cable. A second control pin, VGAIN, is used to adjust broadband
gain to compensate for low frequency flat losses present in the
cable. A third control, VPOLE, is used to move the positions of the
equalizer poles and can be linearly derived from VPEAK, as illustrated
in the Typical Performance Characteristics and Applications
Information sections, for UTP and coaxial cables. Finally, an
output offset adjust control, VOFFSET, allows the designer to shift
the output dc level.
The AD8123 has a high impedance differential input that makes
termination simple and allows dc-coupled signals to be received
directly from the cable. The AD8123 input can also be used in a
single-ended fashion in coaxial cable applications. For differential
systems that require very high CMRR, a triple differential
receiver, such as the AD8143 or AD8145, can be placed in
front of the AD8123.
The AD8123 has a low impedance output that is capable of
driving a 150 Ω load. For systems where the AD8123 has to
drive a high impedance capacitive load, it is recommended that
a small series resistor be placed between the output and load to
buffer the capacitance. The resistor should not be so large as to
reduce the overall bandwidth to an unacceptable level.
Data Sheet
The AD8123 is designed such that systems that use short-to-
medium-length cables do not pay a noise penalty for excess gain
that they do not require. The high gain is only available for
longer length systems where it is required. This feature is built
into the VPEAK control and is transparent to the user.
Two comparators are provided on-chip that can be used for
sync pulse extraction in systems that use sync-on-common
mode encoding. Each comparator has very low output impedance
and can therefore be used in a source-only cable termination
scheme by placing a series resistor equal to the cable characteristic
impedance directly on the comparator output. Additional
details are provided in the Applications Information section.
INPUT COMMON-MODE VOLTAGE RANGE
CONSIDERATIONS
When using the AD8123 as a receiver, it is important to ensure
that its input common-mode voltage stays within the specified
range. The received common-mode level is calculated by adding
the common-mode level of the driver, the single-ended peak
amplitude of the received signal, the amplitude of any sync
pulses, and the other induced common-mode signals, such as
ground shifts between the driver and the AD8123 and pickup
from external sources, such as power lines and fluorescent
lights. See the Applications Information section for more details.
Rev. B | Page 10 of 16
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet AD8123.PDF ] | |
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