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VNS3NV04D-E
OMNIFET II
fully autoprotected Power MOSFET
Features
Max On-State resistance (per ch.) RON 120m
Current limitation (typ)
)Drain-Source clamp voltage
ILIMH
VCLAMP
3.5A
40V
uct(s■ Linear current limitation
rod■ Thermal shut down
P■ Short circuit protection
te■ Integrated clamp
le■ Low current drawn from input pin
so■ Diagnostic feedback through input pin
b■ Esd protection
- O■ Direct access to the gate of the power mosfet
)(analog driving)
roduct(s■ Compatible with standard power mosfet
SO-8
Description
The VNS3NV04D-E is a device formed by two
monolithic OMNIFET II chips housed in a
standard SO-8 package. The OMNIFET II are
designed in STMicroelectronics VIPower M0-3
Technology: they are intended for replacement of
standard Power MOSFETS from DC up to 50KHz
applications. Built in thermal shutdown, linear
current limitation and overvoltage clamp protects
the chip in harsh environments.
Fault feedback can be detected by monitoring the
voltage at the input pin.
Obsolete PTable 1. Device summary
Package
Tube
Tape and Reel
SO-8
VNS3NV04D-E
VNS3NV04DTR-E
September 2013
Rev 3
1/21
www.st.com
21
VNS3NV04D-E
Block diagram and pin description
1 Block diagram and pin description
Figure 1. Block diagram
DRAIN1
DRAIN2
OVERVOLTAGE
CLAMP
OVERVOLTAGE
CLAMP
INPUT1
GATE
CONTROL
GATE
CONTROL
INPUT2
)OVER
uct(sTEMPERATURE
LINEAR
CURRENT
LIMITER
LINEAR
CURRENT
LIMITER
SOURCE1 SOURCE2
OVER
TEMPERATURE
ProdFigure 2. Configuration diagram (top view)
soleteSOURCE 1
bINPUT 1
- OSOURCE 2
Obsolete Product(s)INPUT2
1
4
8 DRAIN 1
DRAIN 1
DRAIN 2
5 DRAIN 2
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VNS3NV04D-E
Figure 7. Input charge test circuit
Electrical specifications
)VIN GEN
Obsolete Product(s) - Obsolete Product(sFigure 8. Unclamped inductive waveforms
ND8003
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