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PDF AD392 Data sheet ( Hoja de datos )
| Número de pieza | AD392 | |
| Descripción | Complete Quad 12-Bit D/A Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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ANALOG
W DEVICES
CompleteQuad12-Bit
OfAConvertewr ithReadback
FEATURES
Data Readback Capability
Four Complete, Voltage Output, 12-Bit DACs in One
32-Pin Hermetic Package
Fast Bus Access: 40ns max, Tmin-Tmax
Asynchronous Reset to Zero Volts
Minimum of Two TTL Load Drive (Readback Mode)
Double-Buffered Data Latches
Monotonicity Guaranteed TminoTmax
Linearity Error :t:1/2LSB
Low Digital-to-Analog Feedthrough, 2nV sec typ
Factory Trimmed Gain and Offset
Low Cost
OBPRODUCT DESCRIPTION
SThe AD392 is a quad I2-bit, high-speed, voltage output digital-to-
Oanalog converter with readback in a 32-pin hermetically sealed
package. The design is based on a custom IC interface to complete
LI2-bit DAC chips which reduces chip count and provides high
reliability. The AD392 is ideal for systems requiring digital
Econtrol of many analog voltages and for the monitoring of these
Tanalog voltages especially where board space is a premium. Such
Eapplications include ATE, robotics, process controllers and
PRODUCT HIGHLIGHTS
1. The AD392 is packaged in a 32-pin DIP and is a complete
solution to space constraint multiple DAC applications.
2. Readback capability provides system monitor of DAC output
useful in ATE, robotics or any closed-loop system.
3. Fast bus access time of 40ns maximum allows for fast system
updating compatible with high-speed microprocessing.
4. Simultaneous reset to zero volts output is extremely useful
precision fIlters.
for system calibration or simply when all DAC outputs must
Featuring maximum access time of 40ns, the AD392 is capable
initially start at zero volts.
of interfacing to the fastest of microprocessors. The readback
capability provides a diagnostic check between the data sent
5. Readback drive capability of two TTL loads virtually eliminates
the need to buffer.
from the microprocessor and the actual data received and trans-
ferred to the DAC. When RESET is low, all four DACs are
simultaneously set to (bipolar) zero providing a known starting
6. Each DAC is independently addressable, providing a versatile
control architecture for simple interface to microprocessors.
point.
7. Monolithic DAC chips provide excellent linearity and guaran-
The AD392 is laser-trimmed to :!:1/2LSB integral linearity and
teed monotonicity over the full operating temperature range.
:!:ILSB max differential linearity at + 25°C. Monotonicity is
guaranteed over the full operating temperature range. The high
initial accuracy and stability over temperature are made possible
by the use of precision thin-fIlm resistors.
The individual DAC registers are accessed by the address lines
AO and Al and control lines CS and 2ND UP. These control
8. Low digital-to-analog feedthrough (2nV sec typ) is maintained
to assure DAC accuracy.
9. New pin stake package provides a low-cost solution to cost
constraint applications.
signals permit the registers of the four DACs to be loaded
sequentially and the outputs to be simultaneously updated.
The AD392 outputs are calibrated for a :!:lOV output range
with positive true offset binary input coding.
The AD392 is packaged in a 32-lead ceramic package and is
hermetically sealed. The AD392 is specified for operation over
the 0 to + 70°C temperature range.
Information furnished by Analog Devices is believed to be accurate
and reliable. However. no responsibility is assumed by Analog Devices
for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implica-
tion or otherwise under any patent or patent rights of Analog Devices.
One Technology Way; P. O. Box 9106; Norwood, MA 02062-9106
Tel: 617/329-4700
TWX:710/394-6577
West Coast
Mid-West
Texas
714/641-9391
3121350-9399
2141231-5094
1 page  
,~() )
TIMING
The timing diagrams (Figures 2 and 3) illustrate the precise
Symbol Parameter
Min Max Unit
relationship between control signals, address signals and the
data. The address lines (CS, AI, AO)as well as the data (DO-Dll)
must be valid a minimum of l5ns before a WR is executed, and
the data must remain valid a minimum of l5ns after the WR
IDS Device Select
tw Write!UpdatelResetPulse Width
tsu Data SetUp Time
tHD Data Hold Time
IRS Reset Valid for Read
IS ns
IS ns
IS ns
IS ns
35 ns
has been executed. Minimum pulse width for the WR, 2ND UP
and RESET commands is l5ns, Similarly, the address lines (CS,
AI, AO)must be valid a minimum of 15ns before a RD is executed.
tVR
tDDS
tBAOn
tBAOff
Read Valid After Write
30 ns
Device De-Select (from Read Data to Tristate
40 ns
Bus Access On Time
40 ns
Bus Access Off Time
30 ns
Data will be valid a maximum of 40ns after RD goes low, (Note: t2L! Minimum Latch Delay after Write/
10 ns
This is a MAXIMUM and, therefore, data should be off the bus
just before RD goes low to avoid bus contention problems, i.e.,
damage to the device, data bus oscillations which may result in
t21.2
t2TR
tnn
tR"tp
Minimum Latch Delay after Next Write!
5
ns
2ND Rank Transparent for Valid Read
25
ns
2ND Rank Transparent to DAC Port Outputs
40 ns
Data Rise, Fall Times
0 5 ns
latching erroneous data in the registers.) Data will be off the
bus a maximum of 30ns after RD goes high. (Note: This is a
NOTES
MAXIMUM and, therefore, the data read should be completed
Timing between pulses measured at 50"A,points.
just before RD goes high to avoid reading erroneous data.)
DAC settling time is measured from the trailing rising edge of
the WR signal.
esj
OA°-i
I BAI -1 tV"
--I tm
S lViR
OL2NDUP
EDATA IN
TEDATA OUT
r
TRISTATE
TRISTATE
Bus access on rime measured from 50% point of read going low to active high (2.4)
or active low (0.4) (see Figures 4 and 5).
Bus access off time measured from 50% point of read going high to point at which voltage
rrails away from active high or low under standard tristate load conditions (see Figure 6).
Table 11/. ACCharactertics: Voo = 5.0V::!::10%;
05TA5+70°C; v,N= VooorDGND
iID
4
'" 3
~
0>
DATA
OUT
RESET
'DATA IS IN BOTH 1" AND 2NO RANKS
uDATA B IS IN 2NORANK. DATA C IS IN 1" RANK
10 20 30 40 50
ns
Figure 4. Typical Bus Access Off Time (tSA Off)
Figure 2. AD392Write/Read Cycle Timing Diagram
DATA
OUT
mJ
:~
IRD
\VA--.:::r::.ON
DATA OUT
IVO BUSI
TRISTATE
I-
--J '" ON
TRISTATE
f
I
I
I
I- 1--'00'--1
)( XRESET CODE
TRISTATE
DATA IN
(lID BUS)
RESET
TRISTATE
¥r-t,,-J
TRISTATE
Figure 3, AD392 Read Cycle Timing Diagram
-5-
'"
~
0
>
RD
10 20 30 40 50
ns
Figure 5. Typical Bus Access On Time (tSA On)
+5V
IHP6216A
VOLTAGE SUPPLY I
RI
TRISTATE
OUTPUT
-TO SCOPE INPUT
TEKTRONIX
7A26 PLUG.IN
P6106A PROBES
7704A MAINFRAME
7B92 TIME BASE
OR EQUIVALENT
==RI 1.35kH ""%,1/4W
R2 1.25kH ""%, 1/4W
=CI 100pF, FOR tBA ON
=R2 15pF, FOR tBA OFF
ALL DIODES IN916
OR EQUIVALENT
DIGITAL
GROUND
Figure 6. Standard Tristate Load Circuit
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet AD392.PDF ] | |
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