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PDF LM2506 Data sheet ( Hoja de datos )
| Número de pieza | LM2506 | |
| Descripción | 18-bit RGB Display Interface Serializer and Deserializer | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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August 2006
LM2506
Low Power Mobile Pixel Link (MPL) Level 0, 18-bit RGB
Display Interface Serializer and Deserializer
General Description
The LM2506 device adapts RGB style display interfaces to
the Mobile Pixel Link (MPL) Level zero serial link. The
LM2506 supports one RGB display at up to 18-bit color
depth and 800 X 300 pixels (over 216 Mbps and 13.2 MHz
PCLK) is supported. A mode pin configures the device as a
Serializer (SER) or Deserializer (DES) so the same chip can
be used on both sides of the interface.
The interconnect is reduced from 22 signals to only 3 active
signals with the LM2506 chipset easing flex interconnect
design, size constraints and cost.
The LM2506 in SER mode resides beside an application,
graphics or baseband processor and translates a parallel
bus from LVCMOS levels to serial Mobile Pixel Link levels for
transmission over a flex cable (or coax) and PCB traces to
the DES located near the display module.
When the Power_Down (PD*) input is asserted on the SER,
the MDn and MC line drivers are powered down to save
current. The DES can be controlled by a separate Power-
_Down input or via a signal from the SER (PDOUT*).
The LM2506 implements the physical layer of the MPL Level
0 Standard (MPL-0) and a 150 µA IB current (Class 0).
Features
n RGB Display Interface support up to
800 x 300 1⁄2SVGA formats
n MPL-Level 0 Physical Layer using two data and one
clock signal
n Low Power Consumption
n Pinout mirroring enables straight through layout with
minimal vias
n Level translation between host and display
n Auto Power Down on STOP PCLK
n Link power down mode reduces quiescent power
under < 10 µA
n 1.74V to 2.0V core / analog supply voltage range
n 1.74V to 3.0V I/O supply voltage range
n −30C to 85C Operating temperature range
System Benefits
n Small Interface
n Low Power
n Low EMI
n Intrinsic Level Translation
Typical Application Diagram - Bridge Chips
© 2006 National Semiconductor Corporation DS201255
20125522
www.national.com
1 page  
Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3)
Symbol
Parameter
Conditions
Min Typ
MPL
IDDZ
PD
Supply Current — Disable
TA = 25˚C
Power Down Modes
Power Dissipation
SER
PD* = L
SER
Stop Clock
DES
PD* = L
RGB
(Note 6)
VDDIO
VDD/VDDA
VDDIO
VDD/VDDA
VDDIO
VDD/VDDA
SER
DES
<1
<1
<1
<1
<1
<1
8.5
15.3
Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2)
Symbol
Parameter
Conditions
Min Typ
PARALLEL BUS TIMING See
tSET
tHOLD
tRISE
Set Up Time
Hold Time
Rise Time
tFALL
Fall Time
SERIAL BUS TIMING
RGB Mode Inputs
5
Figure 11
5
PCLK Output
CL = 15 pF,
Figure 2
VDDIO = 1.74V
VDDIO = 3.0V
VDDIO = 1.74V
VDDIO = 3.0V
7
3
7
2
tDVBC
Serial Data Valid before
Clock
(Set Time)
DES Input
Figure 1
MC = 80MHz
(Note 9)
1.5
tDVAC
Serial Data Valid after
Clock
(Hold Time)
1.5
POWER UP TIMING
t0 SER PLL Lock Counter
4,096
t1 MC Pulse Width Low
180
t2 MC Pulse Width High
180
t3 MC H-L to Active State
180
tPZXclk
Enable Time - Clock Start
RGB Mode
MPL POWER OFF TIMING
tPAZ Disable Time to Power
Down
tPXZclk
Disable Time - Clock Stop
CLK to PDout*
(Note 8)
PCLK to PDOUT*
Figure 3
Figure 4
7
7
Max
2
2.2
2
2.2
2
2.2
Max
12
7
11
6
2
Units
µA
µA
µA
µA
µA
µA
mW
mW
Units
ns
ns
ns
ns
ns
ns
ns
ns
PCLK
cycles
MC
cycles
MC
cycles
MC
cycles
PCLK
cycles
ms
PCLK
cycles
5 www.national.com
5 Page 
Functional Description (Continued)
TABLE 2. Serializer Input Timing Parameters for RGB Interface
Sym.
tSET
tHOLD
Parameter
Data (RGB, DE, VS or HS) to PCLK - Set Time
PCLK to Data (RGB, DE, VS or HS) - Hold Time
Min Typ
5
5
Note 10: Signal rise and fall times are equal to or less than 20ns
Note 11: Measurement of signal timing is made using 0.3 x VDDIO for the low sate and 0.7 x VDDIO for the high state.
Max
Units
ns
ns
20125527
FIGURE 12. Deserializer Mode Output Timing for RGB Interface
Sym.
tDVBC
tDVAC
tPCLK
PCLKLOW
PCLKHIGH
TABLE 3. Deserializer Output Timing Parameters for RGB Interface
Parameter
Data Valid before PCLK (rise) PCLK = 2 MHz
(Note 9)
PCLK = 13.3 MHz
Data Valid after PCLK (rise) PCLK = 2 MHz
(Note 9)
PCLK = 13.3 MHz
Pixel Clock Period
Pixel Clock Low
Pixel Clock High
Min
230
30
230
30
75.2
Typ
50
50
Max
500
Units
ns
ns
ns
ns
ns
%
%
11 www.national.com
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet LM2506.PDF ] | |
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