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PDF XRT7295AE Data sheet ( Hoja de datos )
| Número de pieza | XRT7295AE | |
| Descripción | DS3/Sonet STS-1 Integrated Line Receiver | |
| Fabricantes | Exar Corporation | |
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FEATURES
D Fully Integrated Receive Interface for DS3 and
STS-1 Rate Signals
D Integrated Equalization (Optional) and Timing
Recovery
D Loss-of-Signal and Loss-of-Lock Alarms
D Variable Input Sensitivity Control
D 5V Power Supply
D Pin Compatible with XRT7295AT
D Companion Device to T7296 Transmitter
XRT7295AE
DS3/Sonet STS-1
Integrated Line Receiver
APPLICATIONS
D Interface to DS-3 Networks
D Digital Cross-Connect Systems
D CSU/DSU Equipment
D PCM Test Equipment
D Fiber Optic Terminals
December 2000-2
GENERAL DESCRIPTION
The XRT7295AE DS3/SONET STS-1 integrated line
receiver is a fully integrated receive interface that
terminates a bipolar DS3 (44.736Mbps) or Sonet STS-1
(51.84Mbps) signal transmitted over coaxial cable. (See
Figure 13).
The device also provides the functions of receive
equalization (optional), automatic-gain control (AGC),
clock-recovery and data retiming, loss-of-signal and
loss-of-frequency-lock detection. The digital system
interface is dual-rail, with received positive and negative
1s appearing as unipolar digital signals on separate
output leads. The on-chip equalizer is designed for cable
distances of 0 to 450ft. from the cross-connect frame to
the device. The receive input has a variable input
sensitivity control, providing three different sensitivity
settings, to adapt longer cables. High input sensitivity
allows for significant amounts of flat loss within the
system. Figure 1 shows the block diagram of the device.
The XRT7295AE device is manufactured using linear
CMOS technology. The XRT7295AE is available in a
20-pin plastic SOJ package for surface mounting.
Two versions of the chip are available, one is for either
DS3 or STS-1 operation (the XRT7295AE, this data
sheet), and the other is for E3 operation (the XRT7295AT,
refer to the XRT7295AT data sheet). Both versions are
pin compatible.
For either DS3 or STS-1, an input reference clock at
44.736MHz or 51.84MHz provides the frequency
reference for the device.
ORDERING INFORMATION
Part No.
XRT7295AEIW
Package
20 Lead 300 Mil JEDEC SOJ
Operating
Temperature Range
-40°C to + 85°C
Rev. 1.20
E2000
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017
1 page  
XRT7295AE
System A
XR-T7296
Transmitter
0-450 ft.
0-450 ft.
System B
Cross
Connect
Frame
DSX-3
or STSX-1
Type 728A
Coaxial Cable
XRT7295AT
Receiver
Figure 2. Application Diagram
SYSTEM DESCRIPTION
Receive Path Configurations
In the receive signal path (see Figure 1), the internal
equalizer can be included by setting REQB = 0 or
bypassed by setting REQB = 1. The equalizer bypass
option allows easy interfacing of the XRT7295AE device
into systems already containing external equalizers.
Figure 3 illustrates the receive path options.
In Case 1 of Figure 3, the signal from the DSX-3
cross-connect feeds directly into RIN. In this mode, the
user should set REQB = 0, engaging the equalizer in the
data path.
In Case 2 of Figure 3, external line build-out (LBO) and
equalizer networks precede the XRT7295AE device. In
this mode, the signal at RIN is already equalized, and the
on-chip filters should be bypassed by setting REQB=1.
In applications where the XRT7295AE device is used to
monitor DS3 transmitter outputs directly, the receive
equalizer should be bypassed.
Maximum input amplitude under all conditions is 850mV
pk.
Rev.1.20
5
5 Page 
XRT7295AE
JITTER ACCOMMODATION
Under all allowable operating conditions, the jitter
accommodation of the XRT7295AE device exceeds all
system requirements for error-free operation
(BER<1E-9). The typical (VDD = 5V, T = 25°C, DSX-3
nominal signal level) jitter accommodation for the
XRT7295AE is shown in Figure 10.
FALSE-LOCK IMMUNITY
False-lock is defined as the condition where a PLL
recovered clock obtains stable phase-lock at a frequency
not equal to the incoming data rate. The XRT7295AE
device uses a combination frequency/phase-lock
architecture to prevent false-lock. An on-chip frequency
comparator continuously compares the EXCLK reference
to the PLL clock. If the frequency difference between the
EXCLK and PLL clock exceeds approximately ±0.5%,
correction circuitry forces re-acquisition of the proper
frequency and phase.
ACQUISITION TIME
If a valid input signal is assumed to be already present at
RIN, the maximum time between the application of device
power and error-free operation is 20ms. If power has
already been applied, the interval between the application
of valid data (or the action of valid data following a loss of
signal) and error-free operation is 4ms.
LOSS-OF-LOCK DETECTION
As stated above, the PLL acquisition aid circuitry monitors
the PLL clock frequency relative to the EXCLK frequency.
The RLOL alarm is activated if the difference between the
PLL clock and the EXCLK frequency exceeds
approximately ±0.5%.
This will not occur until at least 250 bit periods after loss of
input data.
1
0
-1
-2
-3
-4
-5
100
PEAK = 0.05dB
f3dB = 205kHz
500 1K 5K 10K 50K100K 500K
Frequency (Hz)
Figure 9. Typical PLL Jitter Transfer
Characteristic
40
10
G.824
1.0
0.1
1
TR-TSY-000499
Category 2
TR-TSY-000499
Category 1
PUB 54014
XRT7295AE Typical
XRT7295AE Typical
Jitter
Frequency
(Hz)
Jitter
Amplitude
(U.I.)
5k
10k
60k
300k
1M
10
5
1
0.5
0.4
10 100 1K 10K 100K
Sinewave Jitter Frequency (Hz)
1000K
Figure 10. Input Jitter Tolerance at DSX-3 Level
Rev.1.20
11
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| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet XRT7295AE.PDF ] | |
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