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PDF XRD9818 Data sheet ( Hoja de datos )
| Número de pieza | XRD9818 | |
| Descripción | 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR | |
| Fabricantes | Exar Corporation | |
| Logotipo |  |
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XRD9818
3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
JUNE 2004
REV. 1.0.1
GENERAL DESCRIPTION
The XRD9818 is a fully integrated, high-performance
analog signal processor/digitizer specifically
designed for use in 3-channel/2-channel/1-channel
CCD/CIS document imaging applications.
Each channel of the XRD9818 includes a Correlated
Double Sampler (CDS), Offset adjustment,
Programmable Gain Amplifier (PGA). After the gain
and offset adjustments the analog inputs are
sequentially sampled and digitized by a 16-bit A/D
converter. The digital output data is available in 8 or
4-bit wide multiplexed format.
The analog front-end can be configured for use in
CCD or CIS data acquisition applications. The CDS
mode of operation supports both line and pixel-clamp
modes and can be used to achieve significant
reduction in system 1/f noise and CCD reset clock
feed-through. Five programmable clamp levels are
available in CCD mode to adjust for CCD signal swing
and reset pulse size. For CIS mode there are 3
selectable reference options, two internally generated
and one external applied reference.
Two PGA ranges, programmable through the serial
port, help interface the XRD9818 to CCD imagers
that have either a 3V or 2V output swings. The range
of 1x to 5x is used for 3V inputs and the range of 1.5x
to 7.5x is used for 2V inputs. Each channel has an
offset range of -180mV to 180mV (1.4mV/step) for
fine adjustment and an additional -100mV to 200mV
(100mV/step) of gross offset adjustment to correct for
any system offsets.
FEATURES
• 16-Bit A/D Converter
• Triple-Channel, 4MSPS Color Scan Mode
• Single-Channel, 8MSPS Monochrome Scan Mode
• Multiplexed 8-Bit or 4-Bit Output Data Formats
• Triple Correlated Double Sampler
• Triple 9-Bit Programmable Gain Amplifier
• Two Programmable Gain Ranges
• Triple 10-Bit Offset Compensation DAC
• -280mV to +380mV Offset Compensation
• 28-pin TSSOP Package
• Internal Voltage Reference
• 3V Operation with 5V Tolerant inputs
• Low Power CMOS: 190mW @ 3.3V (typ), Power
Down 1mW (typ)
APPLICATIONS
• 48-Bit Color Scanners
• High-performance CCD or CIS Color Scanners
• Multifunction Peripherals
• Film Scanners
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
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XRD9818
3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
ELECTRICAL CHARACTERISTICS - XRD9818
AVDD=DVDD=3.3V, ADCLK=12MHZ, PGA GAIN=MIN, PIXEL RATE=4MHZ, TA=25C UNLESS OTHERWISE SPECIFIED
Parameter
Symbol Min
Typ Max Unit
Conditions
Differential Non-Linearity
Integral Non-Linearity
Output Noise Low Gain
Output Noise High Gain
System Offset Low Gain
System Offset High Gain
SYSTEM SPECIFICATIONS (INCLUDES CDS, PGA AND A/D)
DNL -1.0 -0.9/+0.9 2.5
LSB
INL 50 LSB
NMin
15 LSBrms
NMax
34 LSBrms
SOMin
-50
20 100 mV
SOMax
20
mV
PGA Gain = min
PGA Gain = min
PGA Gain = min, GS=0
PGA Gain = max, GS=0
PGA Gain = min
PGA Gain = max
Parameter
Vref(+)
Vref(-)
Delta Vref
[Vref(+) - Vref(-)]
VCMREF
Symbol
CAPP
CAPN
∆VREF
Min Typ Max Unit
VOLTAGE REFERENCE SPECIFICATIONS
1.9 2.2 2.5 V
0.5 0.7 0.9 V
1.25 1.5 1.75 V
VCM
1.05
1.2
1.35 V
Conditions
Parameter
Symbol
Input Switch-On
Resistance
Input Switch-Off
Resistance
Internal Voltage Clamp
Internal Voltage Clamp
Max Reset Pulse
Input Voltage Range
Ron
Roff
Vclmp1
Vclmp2
Vrst
INVR
Min Typ Max
CDS - S/H SPECIFICATIONS
150
Unit
Ω
66 330
MΩ
2.8
3.0
3.125
V
-0.1 0.0 0.1 V
1.5 V
3.0 V
2.0 V
Conditions
Clamp Enabled
Clamp Disabled
CL[2:0]=110
CL[2:0]=001
GS=0
GS=1
5
5 Page 
xr
XRD9818
3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
3.0 REGISTER MAP
INTERNAL REGISTER MAP
Register
Name
RED Gain
GREEN Gain
BLUE Gain
RED Offset
GREEN Offset
BLUE Offset
MODE 1
MODE 2
BSAMPDelay
VSAMPDelay
ADCLKDelay
TEST
Address
Data Bits
A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 msb
lsb
0 0 0 1 msb
lsb
0 0 1 0 msb
lsb
0 0 1 1 COR[1] COR[0] FOR[7] FOR[6] FOR[5] FOR[4] FOR[3] FOR[2] FOR[1] FOR[0]
0 1 0 0 COG[1] COG[0] FOG[7] FOG[6] FOG[5] FOG[4] FOG[3] FOG[2] FOG[1] FOG[0]
0 1 0 1 COB[1] COB[0] FOB[7] FOB[6] FOB[5] FOB[4] FOB[3] FOB[2] FOB[1] FOB[0]
0 1 1 0 CH[2] CH[1] CH[0] GS
LC CCDEN B/N C/R[2] C/R[1] C/R[0]
0 1 1 1 PD OE
Lpol ADCpol Bpol
Vpol
1 0 0 0 BL[4] BL[3] BL[2] BL[1] BL[0] BT[4] BT[3] BT[2] BT[1] BT[0]
1 0 0 1 VL[4] VL[3] VL[2] VL[1] VL[0] VT[4] VT[3] VT[2] VT[1] VT[0]
1 0 1 0 A[4] A[3] A[2] A[1] A[0] DO[4] DO[3] DO[2] DO[1] DO[0]
1011
*
*
*
*
*
*
*
*
*
*
RESET/RB 1 1 1 1 Reset READ
Note: * Exar test bits, do not over write the default values.
Shaded cells represent unused bits.
RB[3] RB[2] RB[1] RB[0]
3.1 PGA Gain Registers
There are three PGA registers for individually programming the gain in the RED, GREEN, and BLUE channels.
Each gain register has 9 bits of resolution. Bits D[9:1] control the gain while bit D0 is N/A (don’t care). The
XRD9818 has two gain ranges to help interface to imagers that have 3V or 2V of output signal swing. The GS
bit, located in the MODE 1 register, defaults to GS=0 for a gain of 1x to 5x or if GS=1 the gain would be 1.5x to
7.5x. The gain range of 1 to 5x (GS=0) is intended for use with imagers that have a 3V output swing, while the
gain range 1.5 to 7.5x is intended for imagers with 2V or less of output swing. The coding for the PGA registers
is straight binary. See “Section 4.3, Programmable Gain” on page 20 for a functional description of the
XRD9818’s gain stage.
GAIN REGISTER SETTINGS
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Gain (V/V) Gain (V/V)
msb
000000000*
…
111111111
lsb N/A w/GS bit = 0* w/GS bit = 1
not
used
1x
…
5x
1.5x
…
7.5x
* Power-on default value
11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet XRD9818.PDF ] | |
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