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PDF XRD64L43 Data sheet ( Hoja de datos )
| Número de pieza | XRD64L43 | |
| Descripción | Dual 10-Bit 40MSPS CMOS ADC | |
| Fabricantes | Exar Corporation | |
| Logotipo |  |
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Preliminary
XRD64L43
Dual 10-Bit 40MSPS CMOS ADC
FEATURES
• 10-Bit Resolution
• Two Monolithic Complete 10-Bit ADCs
• 40 MSPS Conversion Rate
• On-Chip Track-and-Hold
• On-Chip Voltage Reference
• Low 5 pF Input Capacitance
• TTL/CMOS Outputs
• Tri-State Output Buffers
• Single +3.0V Power Supply Operation
• Low Power Dissipation: 200mW-typ @ 2.7V
• Power Down Mode Less Than 5mW
• 75dB Crosstalk (fin=1.0MHz)
• -40°C to +85°C Operation Temperature Range
GENERAL DESCRIPTION
APPLICATIONS
• MedicalImaging
• Instrumentation
• DataAquisitionSystems
• DigitalComunications
July 2003
BENEFITS
• ReductionofComponents
• Reduction of System Cost
• High Performance @ Low Power Dissipation
• Long Term Time and Temperature Stability
The XRD64L43 is two 10-bit, monolithic, 40 MSPS
ADCs. Manufactured using a standard CMOS pro-
cess, the XRD64L43 offers low power, low cost and
excellent performance. The on-chip track-and-hold
amplifier(T/H) and voltage reference (VREF) eliminate
the need for external active components, requiring only
an external ADC conversion clock for the application.
The XRD64L43 analog input can be driven with ease
due to the high input impedance.
The design architecture uses 17 time- interleaved 10-
bit SAR ADCs in each converter to achieve high
conversion rate of 40 MSPS minimum. In order to
insure and maintain accurate 10-bit operation with
respect to time and temperature, XRD64L43 incorpo-
rates an auto-calibration circuit which continuously
adjusts and matches the offset and linearity of each
ADC. This auto-calibration circuit is transparent to the
user after the initial 4.2ms calibration (168,000 initial clock
cycles).
Thepowerdissipationisonly200mWat40MSPSwith+2.7V
power supply.
Thedigitaloutput dataisstraightbinaryformat,andthetri-
state disable function is provided for common bus interface.
The XRD64L43 internal reference provides cost savings
and simplifies the design/development. The output voltage
of the internal reference is set by two external resistors. The
internal reference can be disabled if an external reference is
used for a power savings of 50mW.
ORDERING INFORMATION
Part Number
XRD64L43AIV
Package Type
64-Lead LQFP
Temperature Range
-40°C to +85°C
Rev. P1.00
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017
1 page  
Preliminary
XRD64L43
PIN DESCRIPTION (CONT'D)
Pin #
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Symbol
DGND
DA5
DA6
DA7
DA8
DA9
OTRA
VCMO
DGND
AGND
AVDD
AGND
AGND
VINB-
VINB+
AGND
VINA+
VINA-
AGND
AVDD
AVDD
AGND
AGND
Description
Digital Ground
Digital Output Bit 5 ADC A
Digital Output Bit 6 ADC A
Digital Output Bit 7 ADC A
Digital Output Bit 8 ADC A
Digital Output Bit 9 ADC A
Over Range Digital Output Bit ADC A
Differential Common Mode Voltage Output
Digital Ground
Analog Ground
Analog Supply Voltage
Analog Ground
Analog Ground
Analog Input B(-)
Analog Input B(+)
Analog Ground
Analog Input A(+)
Analog Input A(-)
Analog Ground
Analog Supply Voltage
Analog Supply Voltage
Analog Ground
Analog Ground
Rev. P1.00
5
5 Page 
Preliminary
XRD64L43
Differential Inputs
The XRD64L43 can be used in either differential or
single-ended input mode. For single-ended inputs, see
the Single-Ended Inputs Section. Differential inputs
reduce system noise by removing noise components
common at both input pins. Figure 5. is a simplified
diagram that is used as a common test circuit with our
XRD64L43ES application board. This circuit is used to
evaluate the dynamic performance of the XRD64L43
using differential inputs. Pin 16, DIFF should be held
high to select differential inputs.
Auto-Calibration
The XRD64L43 incorporates an auto-calibration cir-
cuit which continuously adjusts and matches the
offset and linearity of each ADC. This auto-calibra-
tion circuit is transparent to the user after the initial
4.2ms calibration (168,000 initial clock cycles).
Note: To avoid auto-calibration after power down, do
not disable CKIN. CKIN can be slowed down significantly
to save power without losing calibration.
Input A
Input B
Transformer
22
22
50
Transformer
22
22
50
VINA(+)
VINA(-)
VCMO
VINB(+)
VINB(-)
Figure 5. Common Test Circuit for the
Differential Input Mode
SYNCO, Data Valid Delay and Latency
SYNCO is an output pin provided by the XRD64L43.
Valid data is available on the rising edge of SYNCO,
see Figure 6. The Latency for the XRD64L43 is 17
clock cycles.
CKIN
N
N+1 N+2
Valid Data
SYNCO
N-17
tden=20ns
N-16
N-15
tsynco=2ns (typical)
Figure 6. SYNCO, Data Valid Delay and Latency
for the XRD64L43
Rev. P1.00
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet XRD64L43.PDF ] | |
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