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PDF XRT91L32 Data sheet ( Hoja de datos )
| Número de pieza | XRT91L32 | |
| Descripción | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER | |
| Fabricantes | Exar Corporation | |
| Logotipo |  |
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PRELIMINARY
XRT91L32
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
NOVEMBER 2006
GENERAL DESCRIPTION
The XRT91L32 is a fully integrated SONET/SDH
transceiver for SONET/SDH 622.08 Mbps STS-12/
STM-4 or 155.52 Mbps STS-3/STM-1 applications.
The transceiver includes an on-chip Clock Multiplier
Unit (CMU), which uses a high frequency Phase-
Locked Loop (PLL) to generate the high-speed
transmit serial clock from a slower external clock
reference. It also provides Clock and Data Recovery
(CDR) function by synchronizing its on-chip Voltage
Controlled Oscillator (VCO) to the incoming serial
data stream. The internal CDR unit can be disabled
and bypassed in lieu of an externally recovered
received clock from the optical module. Either the
internally recovered clock or the externally recovered
clock can be used for loop timing applications. The
chip provides serial-to-parallel and parallel-to-serial
converters using an 8-bit wide LVTTL system
interface in both receive and transmit directions.
The transmit section includes an option to accept a
REV. 1.0.2
parallel clock signal from the framer/mapper to
synchronize the transmit section timing. The device
can internally monitor Loss of Signal (LOS) condition
and automatically mute received data upon LOS. An
on-chip SONET/SDH frame byte and boundary
detector and frame pulse generator offers the ability
recover SONET/SDH framing and to byte align the
receive serial data stream into the 8-bit parallel bus.
APPLICATIONS
• SONET/SDH-based Transmission Systems
• Add/Drop Multiplexers
• Cross Connect Equipment
• ATM and Multi-Service Switches, Routers and
Switch/Routers
• DSLAMS
• SONET/SDH Test Equipment
• DWDM Termination Equipment
FIGURE 1. BLOCK DIAGRAM OF XRT91L32
XRT91L32
TXDI[7:0]
8
TXPCLK_IO
REFCLKP/N
TTLREFCLK
CDRAUXREFCLK
RXDO[7:0]
RXPCLKO
ENB
ENB
STS-12/STM-4 or STS-3/STM-1
TRANSCEIVER
PISO
(Parallel Input
Serial Output)
Re-Timer
Div by
8
DLOOP
CMU
RLOOPS
SIPO
(Serial Input
Parallel Output)
8
Div by 8
CDR
ALOOP
TXOP/N
RXIP/N
XRXCLKIP/N
Loop Filters
Control Block
Clock Control
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
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STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L32
REV. 1.0.2
FIGURE 14. LOOP TIMING MODE USING INTERNAL CDR OR AN EXTERNAL RECOVERED CLOCK ....................................................... 25
3.6 TRANSMIT SERIAL OUTPUT CONTROL ..................................................................................................... 25
FIGURE 15. TRANSMIT SERIAL OUTPUT INTERFACE BLOCK .............................................................................................................. 25
4.0 DIAGNOSTIC FEATURES ................................................................................................................... 26
4.1 SERIAL REMOTE LOOPBACK ..................................................................................................................... 26
FIGURE 16. SERIAL REMOTE LOOPBACK......................................................................................................................................... 26
4.2 DIGITAL LOCAL LOOPBACK ....................................................................................................................... 26
FIGURE 17. DIGITAL LOCAL LOOPBACK........................................................................................................................................... 26
4.3 ANALOG LOCAL LOOPBACK ...................................................................................................................... 27
FIGURE 18. ANALOG LOCAL LOOPBACK .......................................................................................................................................... 27
4.4 SPLIT LOOPBACK ......................................................................................................................................... 27
FIGURE 19. SPLIT LOOPBACK......................................................................................................................................................... 27
4.5 EYE DIAGRAM ............................................................................................................................................... 28
FIGURE 20. STS-3/STM-1 EYE DIAGRAM ...................................................................................................................................... 28
FIGURE 21. STS-12/STM-4 EYE DIAGRAM .................................................................................................................................... 28
4.6 SONET JITTER REQUIREMENTS ................................................................................................................. 29
4.6.1 JITTER TOLERANCE: ................................................................................................................................................ 29
FIGURE 22. JITTER TOLERANCE MASK............................................................................................................................................ 29
FIGURE 23. XRT91L32 MEASURED JITTER TOLERANCE AT 622.08 MBPS STS-12/STM-4 .............................................................. 30
FIGURE 24. XRT91L32 MEASURED JITTER TOLERANCE AT 155.52 MBPS STS-3/STM-1 ................................................................ 30
4.6.2 JITTER GENERATION................................................................................................................................................ 31
FIGURE 25. XRT91L32 MEASURED ELECTRICAL PHASE NOISE TRANSMIT JITTER GENERATION AT 622.08 MBPS STS-12/STM4 USING
’1010’ OUTPUT PATTERN................................................................................................................................................. 31
5.0 ELECTRICAL CHARACTERISTICS ................................................................................................... 32
ABSOLUTE MAXIMUM RATINGS .................................................................................................................. 32
ABSOLUTE MAXIMUM POWER AND INPUT/OUTPUT RATINGS ......................................................... 32
POWER AND CURRENT DC ELECTRICAL CHARACTERISTICS.................................................................... 32
................................................................................................................................................................... 32
LVPECL AND LVTTL LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS...................................... 33
ORDERING INFORMATION .................................................................................................................. 34
PACKAGE DIMENSIONS ................................................................................................ 34
REVISION HISTORY ...................................................................................................................................... 35
II
5 Page 
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REV. 1.0.2
XRT91L32
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
NAME
CAP1P
CAP2P
CAP1N
CAP2N
DLOSDIS
LOSEXT
LEVEL
Analog
TYPE
-
Analog
-
LVTTL
I
SE-LVPECL
I
PIN DESCRIPTION
63 CDR Non-Inverting External Feeback Capacitor
66 C1 = 0.47μF ± 10% tolerance
(Isolate from noise and place close to pin)
64 CDR Inverting External Feeback Capacitor
65 C2 = 0.47μF ± 10% tolerance
(Isolate from noise and place close to pin)
17 LOS (Los of Signal) Detect Disable
Disables internal LOS monitoring and automatic muting of
RXDO[7:0] upon LOS detection (according to gating shown in
Figure 7.) LOS is declared when a string of 128 consecutive
zeros occur on the line. LOS condition is cleared when the 16
or more pulse transitions is detected for 128 bit period sliding
window.
"Low" = Monitor and Mute received data upon LOS declaration
"High" = Disable internal LOS monitoring (see Figure 7 for logic
operation.)
53 LOS or Signal Detect Input from Optical Module
Active "Low." When active, this pin can force the received data
output bus RXDO[7:0] to a logic state of ’0’ per Figure 7.
"Low" = Forced LOS
"High" = Normal Operation
POWER AND GROUND
NAME
VDD3.3
AVDD3.3_TX
AVDD3.3_RX
VDD_LVPECL
AGND_TX
TYPE
PWR
PWR
PWR
PWR
PWR
PIN DESCRIPTION
2,28,31,49,54,58,76,99
3.3V CMOS Power Supply
VDD3.3 should be isolated from the analog VDD power supplies.
Use a ferrite bead along with an internal power plane separation.
The VDD3.3 power supply pins should have bypass capacitors to
the nearest ground. For best results, refer to Application notes
about general board layout guidelines.
62 Analog 3.3V Transmitter Power Supply
AVDD3.3_TX should be isolated from the digital power supplies.
For best results, use a ferrite bead along with an internal power
plane separation. The AVDD3.3_TX power supply pins should
have bypass capacitors to the nearest ground.
67,,68,69
Analog 3.3V Receiver Power Supply
AVDD3.3_RX should be isolated from the digital power supplies.
For best results, use a ferrite bead along with an internal power
plane separation. The AVDD3.3_RX power supply pins should
have bypass capacitors to the nearest ground.
9,15,21
3.3V Input/Output LVPECL Bus Power Supply
These pins require a 3.3V potential voltage for properly biasing
the Differential LVPECL input and output pins.
59,60
Transmitter Analog Ground for 3.3V Analog Power Supplies
It is recommended that all ground pins of this device be tied
together.
9
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet XRT91L32.PDF ] | |
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