PDF XRT83SL38 Data sheet ( Hoja de datos )

Número de pieza	XRT83SL38
Descripción	OCTAL T1/E1/J1 SH TRANSCEIVER
Fabricantes	Exar Corporation
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No Preview Available ! www.DataSheet4U.com PRELIMINARY XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR OCTOBER 2003 REV. P1.1.0 GENERAL DESCRIPTION The XRT83SL38 is a fully integrated Octal (eight channel) short-haul line interface unit for T1 (1.544Mbps) 100Ω, E1 (2.048Mbps) 75Ω or 120Ω, or J1 110Ω applications. In T1 applications, the XRT83SL38 can generate five transmit pulse shapes to meet the short-haul Digital Cross-Connect (DSX-1) template requirements. It also provides programmable transmit pulse generators for each channel that can be used for output pulse shaping allowing performance improvement over a wide variety of conditions (The arbitrary pulse generators are available in both T1 and E1 modes). The XRT83SL38 provides both a parallel Host microprocessor interface as well as a Hardware mode for programming and control. Both the B8ZS and HDB3 encoding and decoding functions are selectable as well as AMI. An on-chip crystal-less jitter attenuator with a 32 or 64 bit FIFO can be placed either in the receive or the transmit path with loop bandwidths of less than 3Hz. The XRT83SL38 provides a variety of loop-back and diagnostic features as well as transmit driver short circuit detection and receive loss of signal monitoring. It supports internal impedance matching for 75Ω, 100Ω, 110Ω and 120Ω for both transmitter and receiver. In the absence of the power supply, the transmit outputs and receive inputs are tri-stated allowing for redundancy applications The chip includes an integrated programmable clock multiplier that can synthesize T1 or E1 master clocks from a variety of external clock sources. APPLICATIONS • T1 Digital Cross-Connects (DSX-1) • ISDN Primary Rate Interface • CSU/DSU E1/T1/J1 Interface • T1/E1/J1 LAN/WAN Routers • Public switching Systems and PBX Interfaces • T1/E1/J1 Multiplexer and Channel Banks Features (See Page 2) FIGURE 1. BLOCK DIAGRAM OF THE XRT83SL38 T1/E1/J1 LIU (HOST MODE) MCLKE1 MCLKT1 TPOS_n/TDATA_n TNEG_n/CODES_n TCLK_n RCLK_n RNEG_n/LCV_n RPOS_n/RDATA_n RLOS_n HW/HOST WR_R/W RD_DS ALE-AS CS RDY_DTACK INT MASTER CLOCK SYNTHESIZER One of Eight channels, CHANNEL_n - (n= 0:7) QRSS PATTERN GENERATOR HDB3/ B8ZS ENCODER TX/RX JITTER ATTENUATOR TAOS ENABLE TIMING CONTROL DFM DRIVE MONITOR TX FILTER & PULSE SHAPER LINE DRIVER QRSS ENABLE QRSS DETECTOR NETWORK LOOP DETECTOR REMOTE LOOPBACK DIGITAL LOOPBACK LOOPBACK ENABLE HDB3/ B8ZS DECODER TX/RX JITTER ATTENUATOR TIMING & DATA RECOVERY LBO[3:0] PEAK DETECTOR & SLICER NLCD ENABLE LOS DETECTOR AIS DETECTOR EQUALIZER CONTROL LOCAL ANALOG LOOPBACK RX EQUALIZER TEST MICROPROCESSOR CONTROLLER MCLKOUT DMO_n TTIP_n TRING_n TXON_n RTIP_n RRING_n ICT µPTS1 µPTS2 D[7:0] µPCLK A[7:0] RESET Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com 1 page XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR PRELIMINARY REV. P1.1.0 TABLE OF CONTENTS GENERAL DESCRIPTION .................................................................................................. 1 APPLICATIONS .............................................................................................................................................. 1 Figure 1. Block Diagram of the XRT83SL38 T1/E1/J1 LIU (Host Mode) ........................................ 1 Figure 2. Block Diagram of the XRT83SL38 T1/E1/J1 LIU (Hardware Mode) ............................... 2 FEATURES ................................................................................................................................................... 2 ORDERING INFORMATION ............................................................................................................... 3 Figure 3. Pin Out of the XRT83SL38 ................................................................................................ 3 TABLE OF CONTENTS ....................................................................................................... I PIN DESCRIPTION BY FUNCTION .................................................................................... 5 RECEIVE SECTIONS ...................................................................................................................................... 5 TRANSMITTER SECTIONS .............................................................................................................................. 7 MICROPROCESSOR INTERFACE ................................................................................................................... 11 JITTER ATTENUATOR .................................................................................................................................. 14 CLOCK SYNTHESIZER ................................................................................................................................. 14 ALARM FUNCTIONS/REDUNDANCY SUPPORT ............................................................................................... 16 POWER AND GROUND ................................................................................................................................ 20 PINS ONLY AVAILABLE IN BGA PACKAGE .......................................................................................... 21 FUNCTIONAL DESCRIPTION .......................................................................................... 22 MASTER CLOCK GENERATOR ..................................................................................................................... 22 Figure 4. Two Input Clock Source .................................................................................................. 22 Figure 5. One Input Clock Source .................................................................................................. 22 RECEIVER ......................................................................................................................... 23 RECEIVER INPUT ........................................................................................................................................ 23 TABLE 1: MASTER CLOCK GENERATOR ............................................................................................... 23 RECEIVE MONITOR MODE ........................................................................................................................... 24 RECEIVER LOSS OF SIGNAL (RLOS) ........................................................................................................... 24 Figure 6. Simplified Diagram of -15dB T1/E1 Short Haul Mode and RLOS Condition .............. 24 RECEIVE HDB3/B8ZS DECODER ............................................................................................................... 25 RECOVERED CLOCK (RCLK) SAMPLING EDGE ............................................................................................ 25 Figure 7. Simplified Diagram of -29dB T1/E1 Gain Mode and RLOS Condition ......................... 25 Figure 8. Receive Clock and Output Data Timing ........................................................................ 25 JITTER ATTENUATOR .................................................................................................................................. 26 GAPPED CLOCK (JA MUST BE ENABLED IN THE TRANSMIT PATH) ................................................................ 26 TABLE 2: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS ........................................ 26 ARBITRARY PULSE GENERATOR FOR T1 AND E1 .......................................................................................... 27 TRANSMITTER ................................................................................................................. 27 DIGITAL DATA FORMAT ............................................................................................................................... 27 TRANSMIT CLOCK (TCLK) SAMPLING EDGE ................................................................................................ 27 Figure 9. Arbitrary Pulse Segment Assignment ........................................................................... 27 TRANSMIT HDB3/B8ZS ENCODER .............................................................................................................. 28 Figure 10. Transmit Clock and Input Data Timing ........................................................................ 28 TABLE 3: EXAMPLES OF HDB3 ENCODING .......................................................................................... 28 TABLE 4: EXAMPLES OF B8ZS ENCODING ........................................................................................... 28 DRIVER FAILURE MONITOR (DMO) ............................................................................................................. 29 TRANSMIT PULSE SHAPER & LINE BUILD OUT (LBO) CIRCUIT ...................................................................... 29 TABLE 5: RECEIVE EQUALIZER CONTROL AND TRANSMIT LINE BUILD-OUT SETTINGS ........................... 29 TRANSMIT AND RECEIVE TERMINATIONS .................................................................. 30 RECEIVER (CHANNELS 0 - 7) ................................................................................................................... 30 Internal Receive Termination Mode ................................................................................................................. 30 TABLE 6: RECEIVE TERMINATION CONTROL ......................................................................................... 30 Figure 11. Simplified Diagram for the Internal Receive and Transmit Termination Mode ........ 31 I 5 Page XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR PRELIMINARY REV. P1.1.0 SIGNAL NAME TRING_0 TRING_1 TRING_2 TRING_3 TRING_4 TRING_5 TRING_6 TRING_7 TPOS_0 TDATA_0 TPOS_1 TDATA_1 TPOS_2 TDATA_2 TPOS_3 TDATA_3 TPOS_4 TDATA_4 TPOS_5 TDATA_5 TPOS_6 TDATA_6 TPOS_7 TDATA_7 TQFP PIN # 9 11 146 148 44 42 115 113 204 201 164 161 57 60 97 100 BGA LEAD # TYPE DESCRIPTION E2 O Transmitter Ring Output for Channel _0 Negative differential transmit output to the line. F3 Transmitter Ring Output for Channel _1 F15 Transmitter Ring Output for Channel _2 E16 Transmitter Ring Output for Channel _3 P2 Transmitter Ring Output for Channel _4 N4 Transmitter Ring Output for Channel _5 R15 Transmitter Ring Output for Channel _6 P17 Transmitter Ring Output for Channel _7 C5 I Transmitter Positive Data Input for Channel _0 - Dual-Rail mode This signal is the positive-rail input data for transmitter 0. Transmitter 0 Data Input - Single-Rail mode This pin is used as the NRZ input data for transmitter 0. A4 Transmitter Positive Data Input for Channel _1 Transmitter 1 Data Input B14 Transmitter Positive Data Input for Channel _2 Transmitter 2 Data Input D14 Transmitter Positive Data Input for Channel _3 Transmitter 3 Data Input V4 Transmitter Positive Data Input for Channel _4 Transmitter 4 Data Input U5 Transmitter Positive Data Input for Channel _5 Transmitter 5 Data Input V15 Transmitter Positive Data Input for Channel _6 Transmitter 6 Data Input T14 Transmitter Positive Data Input for Channel _7 Transmitter 7 Data Input NOTE: Internally pulled “Low” with a 50kΩ resistor for each channel. 8 11 Page

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