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PDF XRT83L38 Data sheet ( Hoja de datos )
| Número de pieza | XRT83L38 | |
| Descripción | OCTAL T1/E1/J1 LH/SH TRANSCEIVER | |
| Fabricantes | Exar Corporation | |
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XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
JUNE 2004
REV. 1.0.0
GENERAL DESCRIPTION
The XRT83L38 is a fully integrated Octal (eight
channel) long-haul and short-haul line interface unit
for T1 (1.544Mbps) 100Ω, E1 (2.048Mbps) 75Ω or
120Ω, or J1 110Ω applications.
In long-haul applications the XRT83L38 accepts
signals that have been attenuated from 0 to 36dB at
772kHz in T1 mode (equivalent of 0 to 6000 feet of
cable loss) or 0 to 43dB at 1024kHz in E1 mode.
In T1 applications, the XRT83L38 can generate five
transmit pulse shapes to meet the short-haul Digital
Cross-Connect (DSX-1) template requirements as
well as for Channel Service Units (CSU) Line Build
Out (LBO) filters of 0dB, -7.5dB -15dB and -22.5dB
as required by FCC rules. It also provides
programmable transmit pulse generators for each
channel that can be used for output pulse shaping
allowing performance improvement over a wide
variety of conditions (The arbitrary pulse generators
are available in both T1 and E1 modes).
The XRT83L38 provides both a parallel Host
microprocessor interface as well as a Hardware
mode for programming and control.
Both the B8ZS and HDB3 encoding and decoding
functions are selectable as well as AMI. An on-chip
crystal-less jitter attenuator with a 32 or 64 bit FIFO
can be placed either in the receive or the transmit
path with loop bandwidths of less than 3Hz. The
XRT83L38 provides a variety of loop-back and
diagnostic features as well as transmit driver short
circuit detection and receive loss of signal monitoring.
It supports internal impedance matching for 75Ω,
100Ω, 110Ω and 120Ω for both transmitter and
receiver. In the absence of the power supply, the
transmit outputs and receive inputs are tri-stated
allowing for redundancy applications The chip
includes an integrated programmable clock multiplier
that can synthesize T1 or E1 master clocks from a
variety of external clock sources.
APPLICATIONS
• T1 Digital Cross-Connects (DSX-1)
• ISDN Primary Rate Interface
• CSU/DSU E1/T1/J1 Interface
• T1/E1/J1 LAN/WAN Routers
• Public switching Systems and PBX Interfaces
• T1/E1/J1 Multiplexer and Channel Banks
Features (See Page 2)
FIGURE 1 BLOCK DIAGRAM OF THE XRT83L38 T1/E1/J1 LIU (HOST MODE)
MCLKE1
MCLKT1
TPOS_n/TDATA_n
TNEG_n/CODES_n
TCLK_n
RCLK_n
RNEG_n/LCV_n
RPOS_n/RDATA_n
RLOS_n
HW/HOST
WR_R/W
RD_DS
ALE_AS
CS
RDY_DTACK
INT
MASTER CLOCK SYNTHESIZER
One of Eight channels, CHANNEL_n - (n= 0:7)
QRSS
PATTERN
GENERATOR
HDB3/
B8ZS
ENCODER
TX/RX JITTER
ATTENUATOR
TAOS
ENABLE
TIMING
CONTROL
DFM
DRIVE
MONITOR
TX FILTER
& PULSE
SHAPER
LINE
DRIVER
QRSS ENABLE
QRSS
DETECTOR
NETWORK
LOOP
DETECTOR
REMOTE
LOOPBACK
DIGITAL
LOOPBACK
LOOPBACK
ENABLE
HDB3/
B8ZS
DECODER
TX/RX JITTER
ATTENUATOR
TIMING &
DATA
RECOVERY
LBO[3:0]
PEAK
DETECTOR
& SLICER
NLCD ENABLE
LOS
DETECTOR
AIS
DETECTOR
EQUALIZER
CONTROL
LOCAL
ANALOG
LOOPBACK
RX
EQUALIZER
TEST
MICROPROCESSOR CONTROLLER
MCLKOUT
DMO_n
TTIP_n
TRING_n
TXON_n
RTIP_n
RRING_n
ICT
µPTS1
µPTS2
D[7:0]
µPCLK
A[7:0]
RESET
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
5
5 Page 
XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
SIGNAL NAME
RXRES1
RXRES0
TQFP
PIN #
81
82
BGA
LEAD #
TYPE
DESCRIPTION
Receive External Resistor Control Pins - Hardware mode
R10 I Receive External Resistor Control Pin 1:
V10 Receive External Resistor Control Pin 0:
These pins determine the value of the external Receive fixed resistor
according to the following table:
RXRES1
0
0
1
1
RXRES0
0
1
0
1
Required Fixed External
RX Resistor
No External Fixed Resistor
240Ω
210Ω
150Ω
RCLKE
133 J16
µPTS1
133 J16
TRANSMITTER SECTIONS
NOTE: These pins are internally pulled “Low” with a 50kΩ resistor.
I Receive Clock Edge - Hardware mode
Set this pin “High” to sample RPOS_N/RNEG_n on the falling edge of
RCLK_n. With this pin tied “Low”, output data are updated on the rising edge
of RCLK_n.
Microprocessor Type Select Input pin 1 - Host mode
This pin along with µPTS2 (pin 128) is used to select the microprocessor
type. See “Microprocessor Type Select Input Pins - Host Mode:” on page 12.
NOTE: This pin is internally pulled “Low” with a 50kΩ resistor.
SIGNAL NAME
TCLKE
µPTS2
TTIP_0
TTIP_1
TTIP_2
TTIP_3
TTIP_4
TTIP_5
TTIP_6
TTIP_7
TQFP
PIN #
128
128
7
13
144
150
46
40
117
111
BGA
LEAD #
TYPE
DESCRIPTION
L15 I Transmit Clock Edge - Hardware mode
Set this pin “High” to sample transmit input data on the rising edge of
TCLK_n. With this pin tied “Low”, input data are sampled on the falling
edge of TCLK_n.
L15 Microprocessor Type Select Input pin 2 - Host mode
This pin along with µPTS1 (pin 133) selects the microprocessor type. See
“Microprocessor Type Select Input Pins - Host Mode:” on page 12.
NOTE: This pin is internally pulled “Low” with a 50kΩ resistor.
E3 O Transmitter Tip Output for Channel _0
Positive differential transmit output to the line.
G4 Transmitter Tip Output for Channel _1
F17 Transmitter Tip Output for Channel _2
C16 Transmitter Tip Output for Channel _3
R2 Transmitter Tip Output for Channel _4
N2 Transmitter Tip Output for Channel _5
N16 Transmitter Tip Output for Channel _6
P16 Transmitter Tip Output for Channel _7
7
11 Page | ||
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| PDF Descargar | [ Datasheet XRT83L38.PDF ] | |
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