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PDF XRT79L73 Data sheet ( Hoja de datos )
| Número de pieza | XRT79L73 | |
| Descripción | 3-CHANNEL DS3/E3 ATM UNI/PPP COMBO IC | |
| Fabricantes | Exar Corporation | |
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PRELIMINARY
XRT79L73
3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
JUNE 2004
HARDWARE MANUAL
The XRT79L73 is a three channel, ATM UNI/PPP
Physical Layer Processor with integrated DS3/E3
framing controllers and Line Interface Units with Jitter
Attenuators that are designed to support ATM direct
mapping and cell delineation as well as PPP mapping
and Frame processing. For ATM UNI applications,
this device provides the ATM Physical Layer (Physi-
cal Medium Dependent and Transmission Conver-
gence sub-layers) interface for the public and private
networks at DS3/E3 rates. For Clear-Channel Framer
applications, this device supports the transmission
and reception of “user data” via the DS3/E3 payload.
The XRT79L73 includes DS3/E3 Framing, Line
Interface Unit with Jitter Attenuator that supports
mapping of ATM or HDLC framed data. A flexible
parallel microprocessor interface is provided for
configuration and control. Industry standard UTOPIA II
and POS-PHY interface are also provided.
GENERAL FEATURES:
• Integrated T3/E3 Line Interface Unit
• Integrated Jitter Attenuator that can be selected
either in Receive or Transmit path
• Flexible integrated Clock Multiplier that takes single
frequency clock and generates either DS3 or E3
frequency.
• 8/16 bit UTOPIA Level I and II and PPP Multi-PHY
Interface operating at 25, 33 or 50 MHz.
• HDLC Controller that provides the mapping/
extraction of either bit or byte mapped
encapsulated packet from DS3/E3 Frame.
• Contains on-chip 16 cell FIFO (configurable in
depths of 4, 8, 12 or 16 cells), in both the Transmit
(TxFIFO) and Receive Directions (RxFIFO)
• Contains on-chip 54 byte Transmit and Receive
OAM Cell Buffer for transmission, reception and
processing of OAM Cells
• Supports ATM cell or PPP Packet Mapping
• Supports M13 and C-Bit Parity Framing Formats
• Supports DS3/E3 Clear-Channel Framing.
• Includes PRBS Generator and Receiver
• Supports Line, Cell, and PLCP Loop-backs
• Interfaces to 8 Bit wide Intel, Motorola or PowerPC
• Low power 3.3V, 5V Input Tolerant, CMOS
• Available in 456 Lead PBGA Package
• JTAG Interface
LINE INTERFACE UNIT
REV. P1.0.0
• On chip Clock and Data Recovery circuit for high
input jitter tolerance
• Meets E3/DS3 Jitter Tolerance Requirements
• Detects and Clears LOS as per G.775.
• Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation
• Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755 and GR-499-CORE,1995
standards
• Meets ETSI TBR 24 and GR-499 Jitter Transfer
Requirements
• On chip B3ZS/HDB3 encoder and decoder that can
be either enabled or disabled
• On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock
• On chip advanced crystal-less Jitter Attenuator
• Jitter Attenuator can be selected in Receive or
Transmit paths
• 16 or 32 bits selectable FIFO size
• Meets the Jitter and Wander specifications
described in T1.105.03b,ETSI TBR-24, Bellcore
GR-253 and GR-499 standards
• Jitter Attenuator can be disabled
• Maximum power consumption 3.1W
DS3/E3 FRAMER
• DS3 framer supports both M13 and C-bit parity.
• DS3 framer meets ANSI T1.107 and T1.404
standards.
• Detects OOF,LOF,AIS,RDI/FERF alarms.
• Generation and Insertion of FEBE on received
parity errors supported.
• Automatic insertion of RDI/FERF on alarm status.
• E3 framer meets G.832,G.751 standards.
• Framers can be bypassed.
ATM/PPP PROTOCOL PROCESSOR
TRANSMIT CELL PROCESSING
• Extracts ATM cells
• Supports ATM cell payload scrambling
• Maps ATM cells into E3 or DS3 frame
• PLCP frame and mapping of ATM cell streams
RECEIVE CELL PROCESSING
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
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PRELIMINARY
3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L73
REV. P1.0.0
TRANSMIT PAYLOAD DATA INPUT INTERFACE ........................................................ 55
TRANSMIT PAYLOAD DATA INPUT INTERFACE - TIMING REQUIREMENTS..................................... 55
TABLE 9: TIMING INFORMATION FO RTHE TRNASMIT PAYLOAD DATA INPUT INTERFACE BLOCK .......................................................... 55
FIGURE 11. TIMING DIAGRAM FOR THE TRANSMIT PAYLOAD DATA INPUT INTERFACE WHEN THE XRT79L73 IS OPERATING IN BOTH THE DS3
AND LOOP-TIMING MODES .............................................................................................................................................. 56
FIGURE 12. TIMING DIAGRAM FOR THE TRANSMIT PAYLOAD DATA INPUT INTERFACE WHEN THE XRT79L73 IS OPERATING IN BOTH THE DS3
AND LOCAL-TIMING MODES............................................................................................................................................. 57
FIGURE 13. TIMING DIAGRAM FOR THE TRANSMIT PAYLOAD DATA INPUT INTERFACE WHEN THE XRT79L73 IS OPERATING IN BOTH THE DS3/
NIBBLE-PARALLEL AND LOOP-TIMING MODES .................................................................................................................. 57
FIGURE 14. TIMING DIAGRAM FOR THE TRANSMIT PAYLOAD DATA INPUT INTERFACE WHEN THE XRT79L73 IS OPERATING IN BOTH THE DS3/
NIBBLE-PARALLEL AND LOCAL-TIMING MODES ................................................................................................................. 58
TRANSMIT OVERHEAD DATA INPUT INTERFACE...................................................... 59
TRANSMIT OVERHEAD DATA INPUT INTERFACE - TIMING REQUIREMENTS.................................. 59
TABLE 10: TIMING INFORMATION FOR THE TRANSMIT OVERHEAD DATA INPUT INTERFACE BLOCK ..................................................... 59
FIGURE 15. TIMING DIAGRAM FOR THE TRANSMIT OVERHEAD DATA INPUT INTERFACE (METHOD 1 ACCESS) .................................... 61
FIGURE 16. TIMING DIAGRAM FOR THE TRANSMIT OVERHEAD DATA INPUT INTERFACE (METHOD 2 ACCESS) .................................... 61
RECEIVE PAYLOAD DATA OUTPUT INTERFACE ....................................................... 62
RECEIVE PAYLOAD DATA OUTPUT INTERFACE - TIMING REQUIREMENTS ................................... 62
TABLE 11: TIMING INFORMATION FOR THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK ...................................................... 62
FIGURE 17. TIMING DIAGRAM FOR THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE (SERIAL MODE).............................................. 62
FIGURE 18. TIMING DIAGRAM FOR THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE (NIBBLE-PARALLEL MODE) ............................. 63
RECEIVE OVERHEAD DATA OUTPUT INTERFACE .................................................... 64
RECEIVE OVERHEAD DATA OUTPUT INTERFACE - TIMING REQUIREMENTS ................................ 64
AC ELECTRICAL CHARACTERISTICS (CONT.)................................................................................................. 64
FIGURE 19. TIMING DIAGRAM FOR THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE (METHOD 1 - USING RXOHCLK) .................. 65
FIGURE 20. TIMING DIAGRAM FOR THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE (METHOD 2 - USING RXOHENABLE) ............ 65
RECEIVE UTOPIA INTERFACE ...................................................................................... 66
RECEIVE UTOPIA INTERFACE ............................................................................................................... 66
FIGURE 21. TIMING DIAGRAM FOR THE RECEIVE UTOPIA INTERFACE BLOCK .................................................................................. 66
TABLE 12: TIMING INFORMATION FOR THE RECEIVE UTOPIA INTERFACE BLOCK ............................................................................. 66
ORDERING INFORMATION ............................................................................................ 68
PACKAGE DIMENSIONS ................................................................................................ 68
REVISION HISTORY ...................................................................................................................................... 69
B
5 Page 
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PRELIMINARY
3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L73
REV. P1.0.0
PIN #
AD2
Y22
AB4
AC2
W26
AB3
G3
A26
J1
NAME
TxOH1/
TxHDLCDat1_5
TxOH2/
TxHDLCDat2_5
TxOH3/
TxHDLCDat3_5
TxOHIns1/
TxHDLCDat1_4
TxOHIns2/
TxHDLCDat2_4
TxOHIns3/
TxHDLCDat3_4
TxOHClk1
TxOHClk2
TxOHClk3
TYPE
DESCRIPTION
I Transmit Overhead Data Input/Transmit HDLC Controller Data Bit 5 input
pins:
I The function of these input pins depend upon whether or not the XRT79L73 has
been configured to operate in the High-Speed HDLC Controller Mode.
I Non-High Speed HDLC Controller Mode - TxOH:
The Transmit Overhead Data Input Interface accepts overhead via these input
pins, and insert this data into the overhead bit positions within the outbound DS3
or E3 frames. If the TxOHIns input pins are pulled "High", then the Transmit
Overhead Data Input Interface will sample the overhead data, via these input
pins, upon the falling edge of the TxOHClk output signals.
Conversely, if the TxOHIns input pins are NOT pulled "High", then the Transmit
Overhead Data Input Interface block will be inactive and will not accept any over-
head data via the TxOH input pins.
High Speed HDLC Controller Mode - TxHDLCDat_5:
If the XRT79L73 is configured to operate in the High-Speed HDLC Controller
mode, then the local terminal equipment will be provided with a byte-wide Trans-
mit HDLC Controller byte-wide input interface. These input pins will function as
Bit 5 within this byte wide interface.
Data, residing on the Transmit HDLC Controller byte wide input interface, will be
sampled upon the rising edge of the TxHDLCClk output signals.
I Transmit Overhead Data Insert Input/Transmit HDLC Controller Data Bit 4
input pins:
I The function of these input pins depend upon whether or not the XRT79L73 has
been configured to operate in the High-Speed HDLC Controller Mode.
I Non-High Speed HDLC Controller Mode - TxOHIns:
This input pins are used to either enable or disable the Transmit Overhead Data
Input Interface block. If the Transmit Overhead Data Input Interface block is
enabled, then it will accept overhead data from the local terminal equipment via
the TxOH input pins; and insert this data into the overhead bit positions within the
outbound DS3 or E3 data stream.
Conversely, if the Transmit Overhead Data Input Interface block is disabled, then
it will NOT accept overhead data from the local terminal equipment. Pulling
these input pins "High" enables the Transmit Overhead Data Input Interface
block. Pulling these input pins "Low" disables the Transmit Overhead Data Input
Interface block.
High-Speed HDLC Controller Mode - TxHDLCDat_4:
If the XRT79L73 is configured to operate in the High-Speed HDLC Controller
mode, then the local terminal equipment will be provided with a byte-wide Trans-
mit HDLC Controller byte-wide input interface. These input pins will function as
Bit 4 within this byte wide interface.
Data, residing on the Transmit HDLC Controller byte wide input interface, will be
sampled upon the rising edge of the TxHDLCClk output signals.
O Transmit Overhead Clock Output:
O These output pins functions as the Transmit Overhead Data Input Interface clock
O signals. If the user enables the Transmit Overhead Data Input Interface block by
asserting the TxOHIns input pins, then the Transmit Overhead Data Input Inter-
face block will sample and latch the data residing on the TxOH input pins upon
the falling edge of these signals.
NOTE: The Transmit Overhead Data Input Interface block is disabled if the user
has configured the XRT79L73 to operate in the High-Speed HDLC
Controller Mode.
9
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet XRT79L73.PDF ] | |
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