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PDF XRT79L72 Data sheet ( Hoja de datos )
| Número de pieza | XRT79L72 | |
| Descripción | 2-CHANNEL DS3/E3 ATM UNI/PPP COMBO IC | |
| Fabricantes | Exar Corporation | |
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PRELIMINARY
XRT79L72
FEBRUARY 2005
2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
REV. P1.0.2
HARDWARE MANUAL
The XRT79L72 is a two channel, ATM UNI/PPP
Physical Layer Processor with integrated DS3/E3
framing controllers and Line Interface Units with Jitter
Attenuators that are designed to support ATM direct
mapping and cell delineation as well as PPP mapping
and Frame processing. For ATM UNI applications,
this device provides the ATM Physical Layer (Physi-
cal Medium Dependent and Transmission Conver-
gence sub-layers) interface for the public and private
networks at DS3/E3 rates. For Clear-Channel Framer
applications, this device supports the transmission
and reception of “user data” via the DS3/E3 payload.
The XRT79L72 includes DS3/E3 Framing, Line Inter-
face Unit with Jitter Attenuator that supports mapping of
ATM or HDLC framed data. A flexible parallel micropro-
cessor interface is provided for configuration and con-
trol. Industry standard UTOPIA II and POS-PHY inter-
face are also provided.
GENERAL FEATURES:
• Integrated T3/E3 Line Interface Unit
• Integrated Jitter Attenuator that can be selected
either in Receive or Transmit path
• Flexible integrated Clock Multiplier that takes single
frequency clock and generates either DS3 or E3
frequency.
• 8/16 bit UTOPIA Level I and II and PPP Multi-PHY
Interface operating at 25, 33 or 50 MHz.
• HDLC Controller that provides the mapping/extrac-
tion of either bit or byte mapped encapsulated
packet from DS3/E3 Frame.
• Contains on-chip 16 cell FIFO (configurable in
depths of 4, 8, 12 or 16 cells), in both the Transmit
(TxFIFO) and Receive Directions (RxFIFO)
• Contains on-chip 54 byte Transmit and Receive
OAM Cell Buffer for transmission, reception and
processing of OAM Cells
• Supports ATM cell or PPP Packet Mapping
• Supports M13 and C-Bit Parity Framing Formats
• Supports DS3/E3 Clear-Channel Framing.
• Includes PRBS Generator and Receiver
• Supports Line, Cell, and PLCP Loop-backs
• Interfaces to 8 Bit wide Intel, Motorola or PowerPC
• Low power 3.3V, 5V Input Tolerant, CMOS
• Available in 456 Lead PBGA Package
• JTAG Interface
LINE INTERFACE UNIT
• On chip Clock and Data Recovery circuit for high
input jitter tolerance
• Meets E3/DS3 Jitter Tolerance Requirements
• Detects and Clears LOS as per G.775.
• Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation
• Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755 and GR-499-CORE,1995
standards
• Meets ETSI TBR 24 and GR-499 Jitter Transfer
Requirements
• On chip B3ZS/HDB3 encoder and decoder that can
be either enabled or disabled
• On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock
• On chip advanced crystal-less Jitter Attenuator
• Jitter Attenuator can be selected in Receive or
Transmit paths
• 16 or 32 bits selectable FIFO size
• Meets the Jitter and Wander specifications
described in T1.105.03b,ETSI TBR-24, Bellcore
GR-253 and GR-499 standards
• Jitter Attenuator can be disabled
• Maximum power consumption 1.7W
DS3/E3 FRAMER
• DS3 framer supports both M13 and C-bit parity.
• DS3 framer meets ANSI T1.107 and T1.404 stan-
dards.
• Detects OOF,LOF,AIS,RDI/FERF alarms.
• Generation and Insertion of FEBE on received par-
ity errors supported.
• Automatic insertion of RDI/FERF on alarm status.
• E3 framer meets G.832,G.751 standards.
• Framers can be bypassed.
ATM/PPP PROTOCOL PROCESSOR
TRANSMIT CELL PROCESSING
• Extracts ATM cells
• Supports ATM cell payload scrambling
• Maps ATM cells into E3 or DS3 frame
• PLCP frame and mapping of ATM cell streams
RECEIVE CELL PROCESSING
• Extraction of ATM cells from PLCP frame or directly
from E3 or DS3 frame
• Termination of PLCP frame
• Supports payload cell de-scrambling
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
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PRELIMINARY
2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L72
REV. P1.0.2
TRANSMIT PAYLOAD DATA INPUT INTERFACE ........................................................ 55
TRANSMIT PAYLOAD DATA INPUT INTERFACE - TIMING REQUIREMENTS..................................... 55
TABLE 9: TIMING INFORMATION FO RTHE TRNASMIT PAYLOAD DATA INPUT INTERFACE BLOCK .......................................................... 55
FIGURE 11. TIMING DIAGRAM FOR THE TRANSMIT PAYLOAD DATA INPUT INTERFACE WHEN THE XRT79L72 IS OPERATING IN BOTH THE DS3
AND LOOP-TIMING MODES .............................................................................................................................................. 56
FIGURE 12. TIMING DIAGRAM FOR THE TRANSMIT PAYLOAD DATA INPUT INTERFACE WHEN THE XRT79L72 IS OPERATING IN BOTH THE DS3
AND LOCAL-TIMING MODES............................................................................................................................................. 57
FIGURE 13. TIMING DIAGRAM FOR THE TRANSMIT PAYLOAD DATA INPUT INTERFACE WHEN THE XRT79L72 IS OPERATING IN BOTH THE DS3/
NIBBLE-PARALLEL AND LOOP-TIMING MODES .................................................................................................................. 57
FIGURE 14. TIMING DIAGRAM FOR THE TRANSMIT PAYLOAD DATA INPUT INTERFACE WHEN THE XRT79L72 IS OPERATING IN BOTH THE DS3/
NIBBLE-PARALLEL AND LOCAL-TIMING MODES................................................................................................................. 58
TRANSMIT OVERHEAD DATA INPUT INTERFACE...................................................... 59
TRANSMIT OVERHEAD DATA INPUT INTERFACE - TIMING REQUIREMENTS.................................. 59
TABLE 10: TIMING INFORMATION FOR THE TRANSMIT OVERHEAD DATA INPUT INTERFACE BLOCK ..................................................... 59
FIGURE 15. TIMING DIAGRAM FOR THE TRANSMIT OVERHEAD DATA INPUT INTERFACE (METHOD 1 ACCESS) .................................... 61
FIGURE 16. TIMING DIAGRAM FOR THE TRANSMIT OVERHEAD DATA INPUT INTERFACE (METHOD 2 ACCESS) .................................... 61
RECEIVE PAYLOAD DATA OUTPUT INTERFACE ....................................................... 62
RECEIVE PAYLOAD DATA OUTPUT INTERFACE - TIMING REQUIREMENTS ................................... 62
TABLE 11: TIMING INFORMATION FOR THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK ...................................................... 62
FIGURE 17. TIMING DIAGRAM FOR THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE (SERIAL MODE).............................................. 62
FIGURE 18. TIMING DIAGRAM FOR THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE (NIBBLE-PARALLEL MODE) ............................. 63
RECEIVE OVERHEAD DATA OUTPUT INTERFACE .................................................... 64
RECEIVE OVERHEAD DATA OUTPUT INTERFACE - TIMING REQUIREMENTS ................................ 64
AC ELECTRICAL CHARACTERISTICS (CONT.)................................................................................................. 64
FIGURE 19. TIMING DIAGRAM FOR THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE (METHOD 1 - USING RXOHCLK) .................. 65
FIGURE 20. TIMING DIAGRAM FOR THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE (METHOD 2 - USING RXOHENABLE) ............ 65
RECEIVE UTOPIA INTERFACE ...................................................................................... 66
RECEIVE UTOPIA INTERFACE ............................................................................................................... 66
FIGURE 21. TIMING DIAGRAM FOR THE RECEIVE UTOPIA INTERFACE BLOCK .................................................................................. 66
TABLE 12: TIMING INFORMATION FOR THE RECEIVE UTOPIA INTERFACE BLOCK ............................................................................. 66
ORDERING INFORMATION ............................................................................................ 68
PACKAGE DIMENSIONS ................................................................................................ 68
REVISION HISTORY ...................................................................................................................................... 69
II
5 Page 
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PRELIMINARY
2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L72
REV. P1.0.2
PIN #
U5
N24
AF1
W25
U4
N25
NAME
TxFrame_0
TxFrame_1
TxFrameRef_0
TxFrameRef_1
TxInClk_0
TxInClk_1
TYPE
DESCRIPTION
O Transmit End of DS3/E3 Frame Indicator:
O These output pins will pulse "High" for one DS3 or E3 clock period, when the
Transmit Section of the XRT79L72 is processing the last bit of a given DS3 or E3
frame. The implications of these output pins, for each mode of operation, are
described below.
ATM UNI/PPP/High-Speed HDLC Controller Mode:
These output pins serve as an end-of-frame indication to the local terminal
equipment.
Clear-Channel Framer Mode:
If the XRT79L72 is configured to operate in the Clear-Channel Framer mode,
then these output pins serve to alert the Local Terminal Equipment that it needs
to begin transmission of a new DS3 or E3 frame. Hence, the Local Terminal
Equipment uses these output signals to maintain Framing Alignment with the
XRT79L72.
I Transmit DS3/E3 Framer - Framing Alignment Input pin:
I If the the Transmit Section of the XRT79L72 is configured to operate in the
Local-Timing/Frame-Slave Mode, then the Transmit DS3/E3 Framer block will
use these input signals as the Framing Reference.
When the XRT79L72 is configured to operate in this mode any rising edge at
these input pins will cause the Transmit DS3/E3 Framer block to begin its cre-
ation of a new DS3 or E3 frame. Consequently, the user must supply a clock sig-
nal that is equivalent to the DS3 or E3 frame rates to these input pins. Further, it
is imperative that this clock signal be synchronized with the 44.736MHz or
34.368MHz clock signal applied to the TxInClk input pins.
NOTE: These input pins should be tied to GND if they are not to be used as the
Transmit DS3/E3 Framer - Framing Reference input signals.
I Transmit DS3/E3 Framer Block - Timing Reference Signal:
I If the Transmit Section of the XRT79L72 is configured to operate in the Local-
Timing Mode, then it will use this signal as the Timing Reference. If the
XRT79L72 is being operating in the DS3 Mode, then the user is expected to
apply a high-quality 44.736MHz clock signal to these input pins. Likewise, if the
XRT79L72 is being operated in the E3 Mode, then the user is expected to apply
a high-quality 34.368MHz clock signal to these input pins.
A Note for Clear-Channel Framer Operation:
If the user is operating the XRT79L72 device in both the Clear-Channel
Framer and Local-Timing modes, then the user should design or config-
ure the System-Side terminal equipment circuitry, such that "outbound"
DS3 or E3 data will be output, upon the falling edge of TxInClk. The
Transmit Payload Data Input Interface (within the Transmit Section of the
XRT79L72 device) will sample the data, applied to the "TxSer" input pin,
upon the rising edge of TxInClk.
NOTE: This input pin should be tied to GND if the XRT79L72 device is configured
to operate in the "Loop-Timing" Mode.
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| PDF Descargar | [ Datasheet XRT79L72.PDF ] | |
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