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PDF XRT75VL00D Data sheet ( Hoja de datos )
| Número de pieza | XRT75VL00D | |
| Descripción | E3/DS3/STS-1 LINE INTERFACE UNIT | |
| Fabricantes | Exar Corporation | |
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XRT75VL00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
FEBRUARY 2004
GENERAL DESCRIPTION
The XRT75VL00D is a single-channel fully integrated
Line Interface Unit (LIU) with Sonet Desynchronizer
for E3/DS3/STS-1 applications. It incorporates an
independent Receiver, Transmitter and Jitter
Attenuator in a single 52 pin TQFP package.
The XRT75VL00D can be configured to operate in
either E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1
(51.84 MHz) modes. The transmitter can be turned
off (tri-stated) for redundancy support and for
conserving power.
The XRT75VL00D’s differential receiver provides high
noise interference margin and is able to receive the
data over 1000 feet of cable or with up to 12 dB of
cable attenuation.
The XRT75VL00D incorporates an advanced crystal-
less jitter attenuator that can be selected either in the
transmit or receive path. The jitter attenuator
performance meets the ETSI TBR-24 and Bellcore
GR-499 specifications. Also, the jitter attenuator can
be used for clock smoothing in SONET STS-1 to DS3
de-mapping.
The XRT75VL00D provides both Serial
Microprocessor Interface as well as Hardware mode
for programming and control.
The XRT75VL00D supports local, remote and digital
loop-backs. The XRT75VL00D also contains an on-
board Pseudo Random Binary Sequence (PRBS)
generator and detector with the ability to insert and
detect single bit error.
FEATURES
RECEIVER:
• On chip Clock and Data Recovery circuit for high
input jitter tolerance.
• Meets E3/DS3/STS-1
Requirements.
Jitter
Tolerance
• Detects and Clears LOS as per G.775.
• Meets Bellcore GR-499 CORE Jitter Transfer
Requirements.
• Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation.
• Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755 and GR-499-CORE,1995
standards.
• Meets ETSI TBR 24 Jitter Transfer Requirements.
• On chip B3ZS/HDB3 encoder and decoder that can
be either enabled or disabled.
REV. 1.0.3
• On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock.
• Provides low jitter output clock.
TRANSMITTER:
• Compliant with Bellcore GR-499, GR-253 and ANSI
T1.102 Specification for transmit pulse
• Tri-state Transmit output capability for redundancy
applications
• Transmitter can be turned on or off.
JITTER ATTENUATOR:
• On chip advanced crystal-less Jitter Attenuator.
• Jitter Attenuator can be selected in Receive or
Transmit paths.
• 16, 32 or 128 bits selectable FIFO size.
• Meets the Jitter and Wander specifications
described in T1.105.03b,ETSI TBR-24, Bellcore
GR-253 and GR-499 standards.
• Jitter Attenuator can be disabled.
• De-Synchronizer for SONET STS-1 to DS-3
demapping.
CONTROL AND DIAGNOSTICS:
• 5 wire Serial Microprocessor Interface for control
and configuration.
• Supports optional internal Transmit Driver
Monitoring.
• PRBS error counter register to accumulate errors.
• Hardware Mode for control and configuration.
• Supports Local, Remote and Digital Loop-backs.
• Single 3.3 V ± 5% power supply.
• 5 V Tolerant I/O.
• Available in 52 pin TQFP.
• -40°C to 85°C Industrial Temperature Range.
APPLICATIONS
• E3/DS3 Access Equipment.
• DSLAMs.
• Digital Cross Connect Systems.
• CSU/DSU Equipment.
• Routers.
• Fiber Optic Terminals.
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
REV. 1.0.3
XRT75VL00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
4.3.2 Interfacing to the line: ....................................................................................................................... 26
4.4 TRANSMIT DRIVE MONITOR: ............................................................................................................................. 26
Figure 16. Transmit Driver Monitor set-up. ..................................................................................................... 26
4.5 TRANSMITTER SECTION ON/OFF: ...................................................................................................................... 27
5.0 The Receiver Section: ...................................................................................................................... 27
5.1 AGC/EQUALIZER: ............................................................................................................................................ 27
5.1.1 Interference Tolerance: ..................................................................................................................... 27
Figure 17. Interference Margin Test Set up for DS3/STS-1 ........................................................................... 28
Figure 18. Interference Margin Test Set up for E3. ........................................................................................ 28
5.2 CLOCK AND DATA RECOVERY: ......................................................................................................................... 29
5.3 B3ZS/HDB3 DECODER: .................................................................................................................................. 29
5.4 LOS (LOSS OF SIGNAL) DETECTOR: ................................................................................................................ 29
5.4.1 DS3/STS-1 LOS Condition: ................................................................................................................ 29
TABLE 9: INTERFERENCE MARGIN TEST RESULTS .............................................................................................. 29
DISABLING ALOS/DLOS DETECTOR: ......................................................................................................... 30
5.4.2 E3 LOS Condition: ............................................................................................................................. 30
TABLE 10: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF
REQEN (DS3 AND STS-1 APPLICATIONS) ......................................................................................... 30
Figure 19. Loss Of Signal Definition for E3 as per ITU-T G.775 .................................................................... 30
5.4.3 Muting the Recovered Data with LOS condition: ............................................................................ 31
Figure 20. Loss of Signal Definition for E3 as per ITU-T G.775. .................................................................... 31
6.0 Jitter: ................................................................................................................................................. 32
6.1 JITTER TOLERANCE - RECEIVER: ...................................................................................................................... 32
6.1.1 DS3/STS-1 Jitter Tolerance Requirements: ..................................................................................... 32
Figure 21. Jitter Tolerance Measurements ..................................................................................................... 32
6.1.2 E3 Jitter Tolerance Requirements: ................................................................................................... 33
Figure 22. Input Jitter Tolerance For DS3/STS-1 .......................................................................................... 33
Figure 23. Input Jitter Tolerance for E3 ......................................................................................................... 33
6.2 JITTER TRANSFER - RECEIVER/TRANSMITTER: .................................................................................................. 34
6.3 JITTER GENERATION: ....................................................................................................................................... 34
6.4 JITTER ATTENUATOR: ...................................................................................................................................... 34
TABLE 11: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE) ..................................... 34
TABLE 12: JITTER TRANSFER SPECIFICATIONS ................................................................................................... 34
7.0 Serial Host interface: ....................................................................................................................... 35
TABLE 13: JITTER TRANSFER PASS MASKS ....................................................................................................... 35
Figure 24. Jitter Transfer Requirements and Jitter Attenuator Performance .................................................. 35
TABLE 14: FUNCTIONS OF SHARED PINS ............................................................................................................ 36
TABLE 15: REGISTER MAP AND BIT NAMES ....................................................................................................... 36
TABLE 16: REGISTER MAP DESCRIPTION ........................................................................................................... 37
TABLE 17: REGISTER MAP DESCRIPTION - GLOBAL ............................................................................................ 41
8.0 Diagnostic Features: ........................................................................................................................ 43
8.1 PRBS GENERATOR AND DETECTOR: ................................................................................................................ 43
8.2 LOOPBACKS: ............................................................................................................................................... 43
8.2.1 ANALOG LOOPBACK: ....................................................................................................................... 43
Figure 25. PRBS MODE ................................................................................................................................. 43
8.2.2 DIGITAL LOOPBACK: ........................................................................................................................ 44
Figure 26. Analog Loopback ........................................................................................................................... 44
8.2.3 REMOTE LOOPBACK: ....................................................................................................................... 45
8.3 TRANSMIT ALL ONES (TAOS): ................................................................................................................... 45
Figure 27. Digital Loopback ............................................................................................................................ 45
Figure 28. Remote Loopback ......................................................................................................................... 45
Figure 29. Transmit All Ones (TAOS) ............................................................................................................. 46
9.0 THE SONET/SDH DE-SYNC FUNCTION within THE liu ................................................................ 47
9.1 BACKGROUND AND DETAILED INFORMATION - SONET DE-SYNC APPLICATIONS .......................... 47
Figure 30. A Simple Illustration of a DS3 signal being mapped into and transported over the SONET Network
48
9.2 MAPPING/DE-MAPPING JITTER/WANDER ................................................................................................ 49
2
5 Page 
REV. 1.0.3
RECEIVE INTERFACE
PIN #
SIGNAL NAME
25 RxON/
SDI
23 REQEN
36 RxClk
24 RxClkINV/
CS
38 RPOS
XRT75VL00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
TYPE
I
I
O
I
O
DESCRIPTION
Receiver Turn ON Input or Serial Data Input:
Function of this pin depends on whether the XRT75VL00D is configured to
operate in Hardware mode or Host mode.
In Hardware mode, setting this input pin “High” turns on and enables the
Receiver..
NOTES:
1. If the XRT75VL00D is configured in HOST mode, this pin functions as
SDI input pin (please refer to the pin description for Microprocessor
Interface)
2. This pin is internally pulled down.
Receive Equalization Enable Input
Setting this input pin "High" enables the Internal Receive Equalizer. Setting this
pin "Low" disables the Internal Receive Equalizer.
NOTES:
1. This input pin is ignored and may be connected to GND if the
XRT75VL00D is operating in the HOST Mode
2. This pin is internally pulled down.
Receive Clock Output
The Recovered Clock signal from the incoming line signal is output through this
pin.By default, the Receiver Section outputs data via RPOS and RNEG pins on
the rising edge of this clock signal.
Configure the Receiver Section to update data on the RPOS and RNEG pins on
the falling edge of RxClk by doing the following:
a) Operating in Hardware mode, pull the RxClkINV pin to “High”.
b) Operating in Host mode, write a “1” to RxClkINV bit field within the Receive
Control Register.
RxClk INVERT or Chip Select:
Function of this pin depends on whether the XRT75VL00D is configured to
operate in Hardware mode or Host mode.
In Hardware mode, setting this input pin “High” configures the Receiver Sec-
tion to invert the RxClk output signals and outputs the recovered data via
RPOS and RNEG on the falling edge of RxClk.
NOTE: If the XRT75VL00D is configured in HOST mode, this pin functions as
CS input pin (please refer to the pin description for Microprocessor
Interface).
Receive Positive Data Output
This output pin pulses “High" whenever the XRT75VL00D has received a Posi-
tive Polarity pulse in the incoming line signal at the RTIP/RRing inputs.
6
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| PDF Descargar | [ Datasheet XRT75VL00D.PDF ] | |
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