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PDF XRT75R06D Data sheet ( Hoja de datos )
| Número de pieza | XRT75R06D | |
| Descripción | SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT | |
| Fabricantes | Exar Corporation | |
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XRT75R06D
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
DECEMBER 2004
GENERAL DESCRIPTION
The XRT75R06D is a six channel fully integrated Line
Interface Unit (LIU) featuring EXAR’s R3 Technology
(Reconfigurable, Relayless, Redundancy) for E3/
DS3/STS-1 applications. The LIU incorporates 6
independent Receivers, Transmitters and Jitter
Attenuators in a single 217 Lead BGA package.
Each channel of the XRT75R06D can be
independently configured to operate in E3 (34.368
MHz), DS3 (44.736 MHz) or STS-1 (51.84 MHz).
Each transmitter can be turned off and tri-stated for
redundancy support or for conserving power.
The XRT75R06D’s differential receiver provides high
noise interference margin and is able to receive data
over 1000 feet of cable or with up to 12 dB of cable
attenuation.
The XRT75R06D incorporates an advanced crystal-
less jitter attenuator per channel that can be selected
either in the transmit or receive path. The jitter
attenuator performance meets the ETSI TBR-24 and
REV. 1.0.0
Bellcore GR-499 specifications. Also, the jitter
attenuators can be used for clock smoothing in
SONET STS-1 to DS-3 de-mapping.
The XRT75R06D provides a Parallel Microprocessor
Interface for programming and control.
The XRT75R06D supports analog, remote and digital
loop-backs. The device also has a built-in Pseudo
Random Binary Sequence (PRBS) generator and
detector with the ability to insert and detect single bit
error for diagnostic purposes.
APPLICATIONS
• E3/DS3 Access Equipment
• DSLAMs
• Digital Cross Connect Systems
• CSU/DSU Equipment
• Routers
• Fiber Optic Terminals
FIGURE 1. BLOCK DIAGRAM OF THE XRT 75R06D
CS
RD
WR
Addr[7:0]
D[7:0]
PCLK
RDY
INT
Pmode
RESET
RTIP_n
RRing_n
TTIP_n
TRing_n
MTIP_n
MRing_n
DMO_n
ICT
µProcessor Interface
XRT75R06D
XRT75R06D
Peak Detector
AGC/
Equalizer
Slicer
Local
LoopBack
Clock & Data
Recovery
LOS
Detector
Clock
Synthesizer
Jitter
Attenuator
MUX
Remote
LoopBack
HDB3/
B3ZS
Decoder
Line
Driver
Device
Monitor
Tx
Pulse
Shaping
Tx
Control
Timing
Control
Jitter
Attenuator
MUX
HDB3/
B3ZS
Encoder
Channel 0
Channel n...
Channel 5
CLKOUT_n
SFM_en
RLOL_n
E3Clk
DS3Clk
STS-Clk/12M
RxClk_n
RxPOS_n
RxNEG/LCV_n
RLOS_n
TxClk_n
TxPOS_n
TxNEG_n
TxON
PART NUMBER
XRT75R06DIB
ORDERING INFORMATION
PACKAGE
217 Lead BGA
OPERATING TEMPERATURE RANGE
-40°C to +85°C
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
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XRT75R06D
REV. 1.0.0
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
Figure 15. Typical interface between terminal equipment and the XRT75R06D (dual-rail data) ................... 25
Figure 16. Transmitter Terminal Input Timing ................................................................................................ 26
Figure 17. Single-Rail or NRZ Data Format (Encoder and Decoder are Enabled) ......................................... 26
4.2 TRANSMIT CLOCK ............................................................................................................................................ 27
4.3 B3ZS/HDB3 ENCODER ................................................................................................................................... 27
4.3.1 B3ZS Encoding .................................................................................................................................. 27
4.3.2 HDB3 Encoding .................................................................................................................................. 27
Figure 18. Dual-Rail Data Format (encoder and decoder are disabled) ......................................................... 27
Figure 19. B3ZS Encoding Format ................................................................................................................. 27
4.4 TRANSMIT PULSE SHAPER ............................................................................................................................... 28
Figure 21. Transmit Pulse Shape Test Circuit ................................................................................................ 28
4.4.1 Guidelines for using Transmit Build Out Circuit ............................................................................. 28
Figure 20. HDB3 Encoding Format ................................................................................................................ 28
4.5 E3 LINE SIDE PARAMETERS .............................................................................................................................. 29
Figure 22. Pulse Mask for E3 (34.368 mbits/s) interface as per itu-t G.703 ................................................... 29
TABLE 3: E3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS .......................... 30
Figure 23. Bellcore GR-253 CORE Transmit Output Pulse Template for SONET STS-1 Applications ......... 31
TABLE 4: STS-1 PULSE MASK EQUATIONS ........................................................................................................ 31
TABLE 5: STS-1 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-253) . 32
Figure 24. Transmit Ouput Pulse Template for DS3 as per Bellcore GR-499 ................................................ 32
TABLE 7: DS3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-499) .... 33
TABLE 6: DS3 PULSE MASK EQUATIONS ........................................................................................................... 33
4.6 TRANSMIT DRIVE MONITOR .............................................................................................................................. 34
4.7 TRANSMITTER SECTION ON/OFF ....................................................................................................................... 34
Figure 25. Transmit Driver Monitor set-up. ..................................................................................................... 34
5.0 Jitter .................................................................................................................................................. 35
5.1 JITTER TOLERANCE .......................................................................................................................................... 35
5.1.1 DS3/STS-1 Jitter Tolerance Requirements ...................................................................................... 35
Figure 26. Jitter Tolerance Measurements ..................................................................................................... 35
5.1.2 E3 Jitter Tolerance Requirements .................................................................................................... 36
Figure 27. Input Jitter Tolerance For DS3/STS-1 .......................................................................................... 36
Figure 28. Input Jitter Tolerance for E3 ......................................................................................................... 36
5.2 JITTER TRANSFER ............................................................................................................................................ 37
5.3 JITTER ATTENUATOR ........................................................................................................................................ 37
TABLE 8: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE) ....................................... 37
TABLE 9: JITTER TRANSFER SPECIFICATION/REFERENCES ................................................................................. 37
5.3.1 Jitter Generation ................................................................................................................................ 38
TABLE 10: JITTER TRANSFER PASS MASKS ....................................................................................................... 38
Figure 29. Jitter Transfer Requirements and Jitter Attenuator Performance .................................................. 38
6.0 Diagnostic Features ......................................................................................................................... 39
6.1 PRBS GENERATOR AND DETECTOR ................................................................................................................. 39
Figure 30. PRBS MODE ................................................................................................................................. 39
6.2 LOOPBACKS ................................................................................................................................................ 40
6.2.1 ANALOG LOOPBACK ........................................................................................................................ 40
Figure 31. Analog Loopback ........................................................................................................................... 40
6.2.2 DIGITAL LOOPBACK ......................................................................................................................... 41
6.2.3 REMOTE LOOPBACK ........................................................................................................................ 41
Figure 32. Digital Loopback ............................................................................................................................ 41
Figure 33. Remote Loopback ......................................................................................................................... 41
6.3 TRANSMIT ALL ONES (TAOS) .................................................................................................................... 42
Figure 34. Transmit All Ones (TAOS) ............................................................................................................. 42
7.0 Microprocessor interface Block ..................................................................................................... 43
TABLE 11: SELECTING THE MICROPROCESSOR INTERFACE MODE ...................................................................... 43
Figure 35. Simplified Block Diagram of the Microprocessor Interface Block .................................................. 43
7.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ........................................................................................ 44
TABLE 12: XRT75R06D MICROPROCESSOR INTERFACE SIGNALS ...................................................................... 44
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75R06D
REV. 1.0.0
RECEIVE INTERFACE
LEAD # SIGNAL NAME TYPE
DESCRIPTION
A2 RxCLK_0
U2 RXCLK_1
A17 RxCLK_2
U17 RxCLK_3
D8 RxCLK_4
P8 RxCLK_5
O Receive Clock Output - Channel 0:
Receive Clock Output - Channel 1:
Receive Clock Output - Channel 2:
Receive Clock Output - Channel 3:
Receive Clock Output - Channel 4:
Receive Clock Output - Channel 5:
By default, RPOS and RNEG data sampled on the rising edge RxCLK..
Set the RxCLKINV bit to sample RPOS/RNEG data on the falling edge of RxCLK
A1 RPOS_0
U1 RPOS_1
A16 RPOS_2
U16 RPOS_3
D9 RPOS_4
P9 RPOS_5
B2 RNEG_0/
LCV_0
T2 RNEG_1/
LCV_1
B16 RNEG_2/
LCV_2
T16
RNEG_3/
LCV_3
D10 RNEG_4/
LCV_4
P10 RNEG_5/
LCV_5
O Receive Positive Data Output - Channel 0:
Receive Positive Data Output - Channel 1:
Receive Positive Data Output - Channel 2:
Receive Positive Data Output - Channel 3:
Receive Positive Data Output - Channel 4:
Receive Positive Data Output - Channel 5:
NOTE: If the B3ZS/HDB3 Decoder is enabled in Single-rail mode, then the zero
suppression patterns in the incoming line signal (such as: "00V", "000V",
"B0V", "B00V") are removed and replaced with ‘0’.
O Receive Negative Data Output/Line Code Violation Indicator - Chan-
nel 0:
Receive Negative Data Output/Line Code Violation Indicator - Chan-
nel 1:
Receive Negative Data Output/Line Code Violation Indicator - Chan-
nel 2:
Receive Negative Data Output/Line Code Violation Indicator - Chan-
nel 3:
Receive Negative Data Output/Line Code Violation Indicator - Chan-
nel 4:
Receive Negative Data Output/Line Code Violation Indicator - Chan-
nel 5:
In Dual Rail mode, a negative pulse is output through RNEG.
Line Code Violation Indicator - Channel n:
If configured in Single Rail mode then Line Code Violation will be output.
6
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| PDF Descargar | [ Datasheet XRT75R06D.PDF ] | |
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