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PDF XRT75L06D Data sheet ( Hoja de datos )
| Número de pieza | XRT75L06D | |
| Descripción | SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT | |
| Fabricantes | Exar Corporation | |
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XRT75L06D
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
APRIL 2005
GENERAL DESCRIPTION
The XRT75L06D is a six channel fully integrated Line
Interface Unit (LIU) for E3/DS3/STS-1 applications.
The LIU incorporates 6 independent Receivers,
Transmitters and Jitter Attenuators in a single 217
Lead BGA package.
Each channel of the XRT75L06D can be
independently configured to operate in E3 (34.368
MHz), DS3 (44.736 MHz) or STS-1 (51.84 MHz).
Each transmitter can be turned off and tri-stated for
redundancy support or for conserving power.
The XRT75L06D’s differential receiver provides high
noise interference margin and is able to receive data
over 1000 feet of cable or with up to 12 dB of cable
attenuation.
The XRT75L06D incorporates an advanced crystal-
less jitter attenuator per channel that can be selected
either in the transmit or receive path. The jitter
attenuator performance meets the ETSI TBR-24 and
Bellcore GR-499 specifications. Also, the jitter
REV. 1.0.4
attenuators can be used for clock smoothing in
SONET STS-1 to DS-3 de-mapping.
The XRT75L06D provides a Parallel Microprocessor
Interface for programming and control.
The XRT75L06D supports analog, remote and digital
loop-backs. The device also has a built-in Pseudo
Random Binary Sequence (PRBS) generator and
detector with the ability to insert and detect single bit
error for diagnostic purposes.
APPLICATIONS
• E3/DS3 Access Equipment
• DSLAMs
• Digital Cross Connect Systems
• CSU/DSU Equipment
• Routers
• Fiber Optic Terminals
FIGURE 1. BLOCK DIAGRAM OF THE XRT 75L06D
CS
RD
WR
Addr[7:0]
D[7:0]
PCLK
RDY
INT
Pmode
RESET
RTIP_n
RRing_n
TTIP_n
TRing_n
MTIP_n
MRing_n
DMO_n
ICT
µProcessor Interface
XRT75L06D
XRT75L06D
Peak Detector
AGC/
Equalizer
Slicer
Local
LoopBack
Clock & Data
Recovery
LOS
Detector
Clock
Synthesizer
Jitter
Attenuator
MUX
Remote
LoopBack
HDB3/
B3ZS
Decoder
Line
Driver
Device
Monitor
Tx
Pulse
Shaping
Tx
Control
Timing
Control
Jitter
Attenuator
MUX
HDB3/
B3ZS
Encoder
Channel 0
Channel n...
Channel 5
CLKOUT_n
SFM_en
RLOL_n
E3Clk
DS3Clk
STS-Clk/12M
RxClk_n
RxPOS_n
RxNEG/LCV_n
RLOS_n
TxClk_n
TxPOS_n
TxNEG_n
TxON
PART NUMBER
XRT75L06DIB
ORDERING INFORMATION
PACKAGE
217 Lead BGA
OPERATING TEMPERATURE RANGE
-40°C to +85°C
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
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XRT75L06D
REV. 1.0.4
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
3.4 TRANSMIT PULSE SHAPER ............................................................................................................................ 27
FIGURE 20. TRANSMIT PULSE SHAPE TEST CIRCUIT ....................................................................................................................... 27
3.4.1 GUIDELINES FOR USING TRANSMIT BUILD OUT CIRCUIT .................................................................................... 27
3.5 E3 LINE SIDE PARAMETERS .......................................................................................................................... 28
FIGURE 21. PULSE MASK FOR E3 (34.368 MBITS/S) INTERFACE AS PER ITU-T G.703....................................................................... 28
TABLE 3: E3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS ....................................................... 29
FIGURE 22. BELLCORE GR-253 CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1 APPLICATIONS .......................... 30
TABLE 4: STS-1 PULSE MASK EQUATIONS ..................................................................................................................................... 30
TABLE 5: STS-1 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-253) .............................. 31
FIGURE 23. TRANSMIT OUPUT PULSE TEMPLATE FOR DS3 AS PER BELLCORE GR-499 ................................................................... 31
TABLE 6: DS3 PULSE MASK EQUATIONS ........................................................................................................................................ 32
TABLE 7: DS3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-499) ................................. 32
3.6 TRANSMIT DRIVE MONITOR ........................................................................................................................... 33
FIGURE 24. TRANSMIT DRIVER MONITOR SET-UP. ........................................................................................................................... 33
3.7 TRANSMITTER SECTION ON/OFF .................................................................................................................. 33
4.0 JITTER ................................................................................................................................................... 34
4.1 JITTER TOLERANCE........................................................................................................................................ 34
FIGURE 25. JITTER TOLERANCE MEASUREMENTS ........................................................................................................................... 34
4.1.1 DS3/STS-1 JITTER TOLERANCE REQUIREMENTS .................................................................................................. 34
FIGURE 26. INPUT JITTER TOLERANCE FOR DS3/STS-1................................................................................................................ 35
4.1.2 E3 JITTER TOLERANCE REQUIREMENTS................................................................................................................ 35
FIGURE 27. INPUT JITTER TOLERANCE FOR E3 .............................................................................................................................. 35
TABLE 8: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE) .................................................................... 36
4.2 JITTER TRANSFER........................................................................................................................................... 36
TABLE 9: JITTER TRANSFER SPECIFICATION/REFERENCES .............................................................................................................. 36
4.3 JITTER ATTENUATOR ..................................................................................................................................... 36
TABLE 10: JITTER TRANSFER PASS MASKS .................................................................................................................................... 37
FIGURE 28. JITTER TRANSFER REQUIREMENTS AND JITTER ATTENUATOR PERFORMANCE................................................................ 37
4.3.1 JITTER GENERATION.................................................................................................................................................. 37
5.0 DIAGNOSTIC FEATURES..................................................................................................................... 38
5.1 PRBS GENERATOR AND DETECTOR ............................................................................................................ 38
FIGURE 29. PRBS MODE ............................................................................................................................................................. 38
5.2 LOOPBACKS .................................................................................................................................................... 39
5.2.1 ANALOG LOOPBACK.................................................................................................................................................. 39
FIGURE 30. ANALOG LOOPBACK..................................................................................................................................................... 39
5.2.2 DIGITAL LOOPBACK ................................................................................................................................................... 40
FIGURE 31. DIGITAL LOOPBACK...................................................................................................................................................... 40
5.2.3 REMOTE LOOPBACK .................................................................................................................................................. 40
FIGURE 32. REMOTE LOOPBACK .................................................................................................................................................... 40
5.3 TRANSMIT ALL ONES (TAOS) ........................................................................................................................ 41
FIGURE 33. TRANSMIT ALL ONES (TAOS)...................................................................................................................................... 41
6.0 MICROPROCESSOR INTERFACE BLOCK ......................................................................................... 42
TABLE 11: SELECTING THE MICROPROCESSOR INTERFACE MODE ................................................................................................... 42
FIGURE 34. SIMPLIFIED BLOCK DIAGRAM OF THE MICROPROCESSOR INTERFACE BLOCK.................................................................. 42
6.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ............................................................................ 43
TABLE 12: XRT75L06D MICROPROCESSOR INTERFACE SIGNALS ................................................................................................... 43
6.2 ASYNCHRONOUS AND SYNCHRONOUS DESCRIPTION............................................................................. 44
FIGURE 35. ASYNCHRONOUS µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS ........................... 45
TABLE 13: ASYNCHRONOUS TIMING SPECIFICATIONS ...................................................................................................................... 45
FIGURE 36. SYNCHRONOUS µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS ............................. 46
TABLE 14: SYNCHRONOUS TIMING SPECIFICATIONS ........................................................................................................................ 46
FIGURE 37. INTERRUPT PROCESS................................................................................................................................................... 47
6.2.1 HARDWARE RESET: ................................................................................................................................................... 48
TABLE 15: REGISTER MAP AND BIT NAMES .................................................................................................................................... 48
TABLE 16: REGISTER MAP DESCRIPTION - GLOBAL ......................................................................................................................... 49
TABLE 17: REGISTER MAP AND BIT NAMES - CHANNEL N REGISTERS (N = 0,1,2,3,4,5) ................................................................... 49
TABLE 18: REGISTER MAP DESCRIPTION - CHANNEL N ................................................................................................................... 51
7.0 THE SONET/SDH DE-SYNC FUNCTION WITHIN THE LIU ................................................................. 56
7.1 BACKGROUND AND DETAILED INFORMATION - SONET DE-SYNC APPLICATIONS .............................. 56
FIGURE 38. A SIMPLE ILLUSTRATION OF A DS3 SIGNAL BEING MAPPED INTO AND TRANSPORTED OVER THE SONET NETWORK ........ 57
7.2 MAPPING/DE-MAPPING JITTER/WANDER .................................................................................................... 58
7.2.1 HOW DS3 DATA IS MAPPED INTO SONET ............................................................................................................... 58
FIGURE 39. A SIMPLE ILLUSTRATION OF THE SONET STS-1 FRAME .............................................................................................. 59
FIGURE 40. A SIMPLE ILLUSTRATION OF THE STS-1 FRAME STRUCTURE WITH THE TOH AND THE ENVELOPE CAPACITY BYTES DESIGNATED
II
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XRT75L06D
REV. 1.0.4
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
RECEIVE INTERFACE
LEAD #
SIGNAL
NAME
TYPE
DESCRIPTION
A6 RTIP_0
U6 RTIP_1
A13 RTIP_2
U13 RTIP_3
A10 RTIP_4
U10 RTIP_5
I Receive Input - Channel 0:
Receive Input - Channel 1:
Receive Input - Channel 2:
Receive Input - Channel 3:
Receive Input - Channel 4:
Receive Input - Channel 5:
These pins along with RRING receive the bipolar line signal from the Remote
DS3/E3/STS-1 Terminal.
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| PDF Descargar | [ Datasheet XRT75L06D.PDF ] | |
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