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PDF XRT73L06 Data sheet ( Hoja de datos )
| Número de pieza | XRT73L06 | |
| Descripción | SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT | |
| Fabricantes | Exar Corporation | |
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XRT73L06
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
OCTOBER 2003
GENERAL DESCRIPTION
The XRT73L06 is a six channel fully integrated Line
Interface Unit (LIU) for E3/DS3/STS-1 applications.
The LIU incorporates 6 independent Receivers and
Transmitters in a single 217 Lead BGA package.
Each channel of the XRT73L06 can be independently
configured to operate in E3 (34.368 MHz), DS3
(44.736 MHz) or STS-1 (51.84 MHz). Each
transmitter can be turned off and tri-stated for
redundancy support or for conserving power.
The XRT73L06’s differential receiver provides high
noise interference margin and is able to receive data
over 1000 feet of cable or with up to 12 dB of cable
attenuation.
The XRT73L06 provides a Parallel Microprocessor
Interface for programming and control.
REV. 1.0.2
The XRT73L06 supports analog, remote and digital
loop-backs. The device also has a built-in Pseudo
Random Binary Sequence (PRBS) generator and
detector with the ability to insert and detect single bit
error for diagnostic purposes.
APPLICATIONS
• E3/DS3 Access Equipment
• DSLAMs
• Digital Cross Connect Systems
• CSU/DSU Equipment
• Routers
• Fiber Optic Terminals
FIGURE 1. BLOCK DIAGRAM OF THE XRT 73L06
CS
RD
WR
Addr[7:0]
D[7:0]
PCLK
RDY
INT
Pmode
RESET
RTIP_n
RRing_n
TTIP_n
TRing_n
MTIP_n
MRing_n
DMO_n
ICT
µProcessor Interface
XRT73L06
XRT73L06
Peak Detector
AGC/
Equalizer
Slicer
Local
LoopBack
Clock & Data
Recovery
LOS
Detector
Clock
Synthesizer
MUX
Remote
LoopBack
HDB3/
B3ZS
Decoder
Line
Driver
Device
Monitor
Tx
Pulse
Shaping
Tx
Control
Timing
Control
HDB3/
MUX B3ZS
Encoder
Channel 0
Channel n...
Channel 5
CLKOUT_n
SFM_en
RLOL_n
E3Clk
DS3Clk
STS-Clk/12M
RxClk_n
RxPOS_n
RxNEG/LCV_n
RLOS_n
TxClk_n
TxPOS_n
TxNEG_n
TxON
PART NUMBER
XRT73L06IB
ORDERING INFORMATION
PACKAGE
217 Lead BGA
OPERATING TEMPERATURE RANGE
-40°C to +85°C
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
XRT73L06
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
3.3.1 B3ZS Encoding .................................................................................................................................. 26
3.3.2 HDB3 Encoding .................................................................................................................................. 26
Figure 17. Dual-Rail Data Format (encoder and decoder are disabled) ......................................................... 26
Figure 18. B3ZS Encoding Format ................................................................................................................. 26
3.4 TRANSMIT PULSE SHAPER ............................................................................................................................... 27
Figure 20. Transmit Pulse Shape Test Circuit ................................................................................................ 27
3.4.1 Guidelines for using Transmit Build Out Circuit ............................................................................. 27
Figure 19. HDB3 Encoding Format ................................................................................................................ 27
3.5 E3 LINE SIDE PARAMETERS .............................................................................................................................. 28
Figure 21. Pulse Mask for E3 (34.368 mbits/s) interface as per itu-t G.703 ................................................... 28
TABLE 3: E3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS .......................... 29
Figure 22. Bellcore GR-253 CORE Transmit Output Pulse Template for SONET STS-1 Applications ......... 30
TABLE 4: STS-1 PULSE MASK EQUATIONS ........................................................................................................ 30
TABLE 5: STS-1 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-253) . 31
Figure 23. Transmit Ouput Pulse Template for DS3 as per Bellcore GR-499 ................................................ 31
TABLE 7: DS3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-499) .... 32
TABLE 6: DS3 PULSE MASK EQUATIONS ........................................................................................................... 32
3.6 TRANSMIT DRIVE MONITOR .............................................................................................................................. 33
3.7 TRANSMITTER SECTION ON/OFF ....................................................................................................................... 33
Figure 24. Transmit Driver Monitor set-up. ..................................................................................................... 33
4.0 Jitter .................................................................................................................................................. 34
4.1 JITTER TOLERANCE .......................................................................................................................................... 34
4.1.1 DS3/STS-1 Jitter Tolerance Requirements ...................................................................................... 34
Figure 25. Jitter Tolerance Measurements ..................................................................................................... 34
4.1.2 E3 Jitter Tolerance Requirements .................................................................................................... 35
Figure 26. Input Jitter Tolerance For DS3/STS-1 .......................................................................................... 35
Figure 27. Input Jitter Tolerance for E3 ......................................................................................................... 35
4.2 JITTER TRANSFER ............................................................................................................................................ 36
TABLE 8: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE) ....................................... 36
TABLE 9: JITTER TRANSFER SPECIFICATION/REFERENCES ................................................................................. 36
TABLE 10: JITTER TRANSFER PASS MASKS ....................................................................................................... 36
4.2.1 Jitter Generation ................................................................................................................................ 37
Figure 28. Jitter Transfer Requirements and Jitter Attenuator Performance .................................................. 37
5.0 Diagnostic Features ......................................................................................................................... 38
5.1 PRBS GENERATOR AND DETECTOR ................................................................................................................. 38
Figure 29. PRBS MODE ................................................................................................................................. 38
5.2 LOOPBACKS ................................................................................................................................................ 39
5.2.1 ANALOG LOOPBACK ........................................................................................................................ 39
Figure 30. Analog Loopback ........................................................................................................................... 39
5.2.2 DIGITAL LOOPBACK ......................................................................................................................... 40
5.2.3 REMOTE LOOPBACK ........................................................................................................................ 40
Figure 31. Digital Loopback ............................................................................................................................ 40
Figure 32. Remote Loopback ......................................................................................................................... 40
5.3 TRANSMIT ALL ONES (TAOS) .................................................................................................................... 41
Figure 33. Transmit All Ones (TAOS) ............................................................................................................. 41
6.0 Microprocessor interface Block ..................................................................................................... 42
TABLE 11: SELECTING THE MICROPROCESSOR INTERFACE MODE ...................................................................... 42
Figure 34. Simplified Block Diagram of the Microprocessor Interface Block .................................................. 42
6.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ........................................................................................ 43
TABLE 12: XRT73L06 MICROPROCESSOR INTERFACE SIGNALS ......................................................................... 43
6.2 ASYNCHRONOUS AND SYNCHRONOUS DESCRIPTION ......................................................................................... 44
TABLE 13: ASYNCHRONOUS TIMING SPECIFICATIONS ......................................................................................... 45
Figure 35. Asynchronous µP Interface Signals During Programmed I/O Read and Write Operations ........... 45
Figure 36. Synchronous µP Interface Signals During Programmed I/O Read and Write Operations ............ 46
TABLE 14: SYNCHRONOUS TIMING SPECIFICATIONS ........................................................................................... 46
Figure 37. Interrupt process ........................................................................................................................... 47
II
5 Page 
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L06
REV. 1.0.2
CLOCK INTERFACE
LEAD #
E15
G16
C16
L15
B1
T1
B17
T17
D11
P11
SIGNAL NAME TYPE
DESCRIPTION
E3CLK
I E3 Clock Input (34.368 MHz ± 20 ppm):
If any of the channels is configured in E3 mode, a reference clock 34.368 MHz
is applied on this pin.
NOTE: In single frequency mode, this reference clock is not required.
DS3CLK
I DS3 Clock Input (44.736 MHz ± 20 ppm):
If any of the channels is configured in DS3 mode, a reference clock 44.736
MHz. is applied on this pin.
NOTE: In single frequency mode, this reference clock is not required.
STS-1CLK/
12M
I STS-1 Clock Input (51.84 MHz ± 20 ppm):
If any of the channels is configured in STS-1 mode, a reference clock 51.84
MHz is applied on this pin..
In Single Frequency Mode, a reference clock of 12.288 MHz ± 20 ppm is con-
nected to this pin and the internal clock synthesizer generates the appropriate
clock frequencies based on the configuration of the channels in E3, DS3 or
STS-1 modes.
SFM_EN
I Single Frequency Mode Enable:
Tie this pin “High” to enable the Single Frequency Mode. A reference clock of
12.288 MHz ± 20 ppm is applied.
In the Single Frequency Mode (SFM) a low jitter output clock is provided for
each channel if the CLK_EN bit is set thus eliminating the need for a separate
clock source for the framer.
Tie this pin “Low” if single frequency mode is not selected. In this case, the
appropriate reference clocks must be provided.
NOTE: This pin is internally pulled down
CLKOUT_0
CLKOUT_1
CLKOUT_2
CLKOUT_3
CLKOUT_4
CLKOUT_5
O Clock output for channel 0
Clock output for channel 1
Clock output for channel 2
Clock output for channel 3
Clock output for channel 4
Clock output for channel 5
Low jitter clock output for each channel based on the mode selection (E3,DS3
or STS-1) if the CLKOUTEN_n bit is set in the control register.
This eliminates the need for a separate clock source for the framer.
NOTES:
1. The maximum drive capability for the clockouts is 16 mA.
2. This clock out is available both in SFM and non-SFM modes.
8
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| PDF Descargar | [ Datasheet XRT73L06.PDF ] | |
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