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PDF XRT73L02M Data sheet ( Hoja de datos )
| Número de pieza | XRT73L02M | |
| Descripción | TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT | |
| Fabricantes | Exar Corporation | |
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XRT73L02M
MAY 2003
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.0
GENERAL DESCRIPTION
The XRT73L02M is a two-channel fully integrated
Line Interface Unit (LIU) for E3/DS3/STS-1 applica-
tions. It incorporates independent Receivers, Trans-
mitters in a single 100 pin TQFP package.
The XRT73L02M can be configured to operate in ei-
ther E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1
(51.84 MHz) modes.The transmitter can be turned off
or tri-stated for redundancy support and for conserv-
ing power.
The XRT73L02M’s differential receiver provides high
noise interference margin and is able to receive the
data over 1000 feet of cable or with up to 12 dB of ca-
ble attenuation.
The XRT73L02M provides both Serial Microproces-
sor Interface as well as Hardware mode for program-
ming and control.
The XRT73L02M supports local,remote and digital
loop-backs. The XRT73L02M also contains an on-
board Pseudo Random Binary Sequence (PRBS)
generator and detector with the ability to insert and
detect single bit error.
FEATURES
RECEIVER:
• On chip Clock and Data Recovery circuit for high
input jitter tolerance.
• Meets the jitter tolerance requirements as specified
in ITU-T G.823_1993 for E3 and Telcordia GR-499-
CORE for DS3 applications.
• Detects and Clears LOS as per G.775.
• Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation.
• On chip B3ZS/HDB3 encoder and decoder that can
either be enabled or disabled.
• On-chip clock synthesizer generates the appropri-
ate rate clock from a single frequency XTAL.
• Provides low jitter clock outputs for either DS3,E3
or STS-1 rates.
• On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock.
• Provides low jitter output clock.
TRANSMITTER:
• Compliant with Bellcore GR-499, GR-253 and ANSI
T1.102 Specification for transmit pulse
• Tri-state Transmit output capability for redundancy
applications
• Transmitter can be turned on or off.
CONTROL AND DIAGNOSTICS:
• 5 wire Serial Microprocessor Interface for control
and configuration.
• Supports optional internal Transmit Driver Monitor-
ing.
• PRBS error counter register to accumulate errors.
• Hardware Mode for control and configuration.
• Supports Local, Remote and Digital Loop-backs.
• Single 3.3 V ± 5% power supply.
• 5 V Tolerant I/O.
• Available in 100 pin TQFP.
• -40°C to 85°C Industrial Temperature Range.
APPLICATIONS
• E3/DS3 Access Equipment.
• STS1-SPE to DS3 Mapper.
• DSLAMs.
• Digital Cross Connect Systems.
• CSU/DSU Equipment.
• Routers.
• Fiber Optic Terminals.
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
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XRT73L02M
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.0
Figure 17. Interference Margin Test Set up for DS3/STS-1 ........................................................................... 32
Figure 18. Interference Margin Test Set up for E3. ........................................................................................ 32
TABLE 9: INTERFERENCE MARGIN TEST RESULTS .............................................................................................. 32
5.0.2 Clock and Data Recovery: ................................................................................................................. 33
5.0.3 B3ZS/HDB3 Decoder: ........................................................................................................................ 33
5.0.4 LOS (Loss of Signal) Detector: ......................................................................................................... 34
DISABLING ALOS/DLOS DETECTION: ......................................................................................................... 34
TABLE 10: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF
LOSTHR AND REQEN (DS3 AND STS-1 APPLICATIONS) ................................................................... 34
Figure 19. Loss Of Signal Definition for E3 as per ITU-T G.775 .................................................................... 35
Figure 20. Loss of Signal Definition for E3 as per ITU-T G.775. .................................................................... 35
6.0 Jitter: ................................................................................................................................................. 36
6.0.1 Jitter Tolerance - Receiver: ............................................................................................................... 36
Figure 21. Jitter Tolerance Measurements ..................................................................................................... 36
Figure 22. Input Jitter Tolerance For DS3/STS-1 .......................................................................................... 37
Figure 23. Input Jitter Tolerance for E3 ......................................................................................................... 37
6.0.2 Jitter Transfer - Receiver/Transmitter: ............................................................................................. 38
TABLE 11: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE) ..................................... 38
TABLE 12: JITTER TRANSFER SPECIFICATION/REFERENCES ............................................................................... 38
TABLE 13: JITTER TRANSFER PASS MASKS ....................................................................................................... 39
Figure 24. Jitter Transfer Requirements and Jitter Attenuator Performance .................................................. 39
6.1.1 Jitter Generation: ............................................................................................................................... 40
7.0 Serial Host interface: ....................................................................................................................... 40
TABLE 14: FUNCTIONS OF SHARED PINS ............................................................................................................ 40
TABLE 15: REGISTER MAP AND BIT NAMES ....................................................................................................... 40
TABLE 16: REGISTER MAP DESCRIPTION - GLOBAL ............................................................................................ 41
TABLE 17: REGISTER MAP AND BIT NAMES - CHANNEL 0 REGISTERS ................................................................. 42
TABLE 18: REGISTER MAP AND BIT NAMES - CHANNEL 1 REGISTERS ................................................................. 42
TABLE 20: REGISTER MAP DESCRIPTION ........................................................................................................... 43
8.0 Diagnostic Features: ........................................................................................................................ 47
8.1 PRBS GENERATOR AND DETECTOR: ................................................................................................................ 47
8.2 LOOPBACKS: ............................................................................................................................................... 48
8.2.1 ANALOG LOOPBACK: ....................................................................................................................... 48
Figure 25. PRBS MODE ................................................................................................................................. 48
8.2.2 DIGITAL LOOPBACK: ........................................................................................................................ 49
Figure 26. Analog Loopback ........................................................................................................................... 49
8.2.3 REMOTE LOOPBACK: ....................................................................................................................... 50
Figure 27. Digital Loopback ............................................................................................................................ 50
8.3 TRANSMIT ALL ONES (TAOS): ................................................................................................................... 51
Figure 28. Remote Loopback ......................................................................................................................... 51
Figure 29. Transmit All Ones (TAOS) ............................................................................................................. 51
APPENDIX ......................................................................................................................... 52
Figure 30. EVALUATION BOARD SCHEMATICS ......................................................................................... 52
Figure 31. Evaluation Board Schematics ....................................................................................................... 53
ORDERING INFORMATION ................................................................................................................ 54
PACKAGE DIMENSIONS - 14X20 MM, 100PIN PACKAGE ................................................................................ 54
REVISIONS ................................................................................................................................................. 55
V
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TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L02M
REV. 1.0.0
CONTROL AND ALARM INTERFACE
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
73 MRING_0
53 MRING_1
I Monitor Ring Input - Channel 0:
Monitor Ring Input - Channel 1:
The bipolar line output signal from TRING_n is connected to this pin via a 270 Ω
resistor to check for line driver failure.
NOTE: This pin is internally pulled "High".
72 MTIP_0
54 MTIP_1
I Monitor Tip Input - Channel 0:
Monitor Tip Input - Channel 1:
The bipolar line output signal from TTIP_n is connected to this pin via a 270-
ohm resistor to check for line driver failure.
NOTE: This pin is internally pulled "High".
79 DMO_0
47 DMO_1
94 RLOS_0
33 RLOS_1
95 RLOL_0
32 RLOL_1
11 RXA
12 RXB
O Drive Monitor Output - Channel 0:
Drive Monitor Output - Channel 1:
If MTIP_n and MRING_n has no transition pulse for 128 ± 32 TxCLK_n cycles,
DMO_n goes “High” to indicate the driver failure. DMO_n output stays “High”
until the next AMI signal is detected.
O Receive Loss of Signal Output Indicator - Channel 0:
Receive Loss of Signal Output Indicator - Channel 1:
This output pin toggles "High" if the receiver has detected a Loss of Signal Con-
dition.
The criteria for declaring /clearing an LOS Condition depends upon whether it is
operating in the E3 or STS-1/DS3 Mode.
O Receive Loss of Lock Output Indicator - Channel 0:
Receive Loss of Lock Output Indicator - Channel 1:
This output pin toggles "High" if a Loss of Lock Condition is detected. LOL
(Loss of Lock) condition occurs if the recovered clock frequency deviates from
the Reference Clock frequency (available at either E3CLK or DS3CLK or STS-
1CLK input pins) by more than 0.5%.
**** External Resistor of 3 K Ω ± 1%.
Should be connected between RxA and RxB for internal bias.
**** External Resistor of 3K Ω ±1%.
Should be connected between RxA and RxB for internal bias.
98 ICT
96 TEST
I In-Circuit Test Input:
Setting this pin "Low" causes all digital and analog outputs to go into a high-
impedance state to allow for in-circuit testing. For normal operation, tie this pin
"High".
NOTE: This pin is internally pulled “High".
**** Factory Test Pin
NOTE: This pin must be connected to GND for normal operation.
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