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PDF XR19L400 Data sheet ( Hoja de datos )
| Número de pieza | XR19L400 | |
| Descripción | SINGLE CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER | |
| Fabricantes | Exar Corporation | |
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PRELIMINARY
XR19L400
SINGLE CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
APRIL 2007
REV. P1.0.0
GENERAL DESCRIPTION
The XR19L400 (L400) is a highly integrated device that
combines a full-featured single channel Universal
Asynchronous Receiver and Transmitter (UART) and RS-
485 transceivers. The L400 is designed to operate with a
3.3V to 5V power supply. The L400 is fully compliant with
RS-485 Standards.
The L400 operates in four different modes: Active, Partial
Sleep, Full Sleep and Power-Save. Each mode can be
invoked via hardware or software. Upon power-up, the
L400 is in the Active mode where the UART and RS-485
transceiver function normally. In the Partial Sleep mode, the
internal crystal oscillator of the UART or charge pump of the
RS-485 transceiver is turned off. In Full Sleep mode, both
the crystal oscillator and the charge pump are turned off.
While the UART is in the Sleep mode, the Power-Save
mode isolates the core logic from the control signals (chip
select, read/write strobes, address and data bus lines) to
minimize the power consumption. The RS-485 receivers
remain active in any of these four modes.
APPLICATIONS
• Battery-Powered Equipment
• Handheld and Mobile Devices
• Handheld Terminals
• Industrial Peripheral Interfaces
• Point-of-Sale (POS) Systems
FEATURES
• Meets true RS-485 Standards from +3.0V to +5.5V
operation
• Up to 8 Mbps data transmission rate
• 45us sleep mode exit (charge pump to full power)
• ESD protection for RS-485 I/O pins at
■ +/-15kV - Human Body Model
■ +/- 8kV - IEC 61000-4-2, Contact Discharge
■ +/- 15kV - IEC 61000-4-2, Air-Gap Discharge
• Software compatible with industry standard 16550 UART
• Intel/Motorola bus select
• Complete modem interface
• Sleep and Power-save modes to conserve battery power
• Wake-up interrupt upon exiting low power modes
FIGURE 1. BLOCK DIAGRAM
PwrSave
A2:A0
D7:D0
IOR#
IOW# (R/W#)
CS# (CS#)
INT (IRQ#)
RESET (RESET#)
I/M#
HALF/FULL#
*5 V Tolerant
Inputs
Crystal
Osc/Buffer
BRG
64 Byte
TX FIFO
TX
Charge Pump
UART
64 Byte
RX FIFO
Modem
I/Os
RX
VCC33
CTS#
DSR#
RI#
CD#
RS-485 Transceiver
XR19L400
TX+
TX-
RX+
RX-
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
PRELIMINARY
XR19L400
REV. P1.0.0
SINGLE CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
1.0 PRODUCT DESCRIPTION
The XR19L400 consists of a single channel UART and RS-485 transceivers. It operates from a single +3V to
5.5V supply with data rates up to 8Mbps, while meeting all EIA/TIA-485 specifications. Its feature set is fully
compatible to the XR16V2751 device. Unlike the XR16V2751, most of the modem signals are not CMOS/TTL
level, but conform to RS-485 voltage levels. The configuration register set is 16550 UART compatible for
control, status and data transfer. Also, the L400 has 64-bytes of transmit and receive FIFOs, automatic RTS/
CTS hardware flow control, automatic Xon/Xoff and special character software flow control, transmit and
receive FIFO trigger levels, and a programmable fractional baud rate generator with a prescaler of divide by 1
or 4. Additionally, the L400 includes the ACP pin which the user can shut down the charge pump for the RS-
485 drivers. In the UART portion, the Power-Save feature isolates the databus interface to further reduce
power consumption in the Sleep mode. The L400 is fabricated using an advanced CMOS process.
Enhanced Features
The L400 UART provides a solution that supports 64 bytes of transmit and receive FIFO. Increased
performance is realized in the L400 by the transmit and receive FIFOs, FIFO trigger level controls and
automatic flow control mechanism. This allows the external processor to handle more networking tasks within
a given time. This increases the service interval giving the external CPU additional time for other applications
and reducing the overall UART interrupt servicing time. In addition, the L400 provides the ACP and Power-
Save modes that drastically reduces the power consumption when the device is not used. The combination of
the above greatly reduces the CPU’s bandwidth requirement, increases performance, and reduces power
consumption.
Intel or Motorola Data Bus Interface
The L400 provides a host interface that supports Intel or Motorola microprocessor (CPU) data bus interface.
The Intel bus compatible interface allows direct interconnect to Intel compatible type of CPUs using IOR#,
IOW# and CS# inputs for data bus operation. The Motorola bus compatible interface instead uses the R/W#
and CS# signals for data bus transactions. See pin description section for details on all the control signals. The
Intel and Motorola bus interface selection is made through the pin, I/M#.
Data Rate
The L400 is capable of operation up to 8 Mbps data rate. The device can operate either with a crystal on pins
XTAL1 and XTAL2, or external clock source on XTAL1 pin.
Internal Enhanced Register Sets
The L400 UART has a set of enhanced registers providing control and monitoring functions. Interrupt enable/
disable and status, FIFO enable/disable, selectable TX and RX FIFO trigger levels, automatic hardware/
software flow control enable/disable, programmable baud rates, modem interface controls and status, sleep
mode and infrared mode are all standard features. Following a power on reset or an external reset (and
operating in 16 or Intel Mode), the registers default to the reset condition and is compatible with the
XR16V2751.
RS-485 Interface
The L402 includes RS-485 drivers/receivers for the interface. This feature eliminates the need for an external
RS-485 transceiver. The RS-485 transceiver can be selected to operate in either the half-duplex or full-duplex
mode via the HALF/FULL# pin. The RS-485 drivers guarantee a data rate of up to 8 Mbps.
All RS-485 drivers and receivers are protected to ±15kV using the Human Body Model ground combination,
±8kV using IEC 61000-4-2 Contact Discharge, and ±15kV using IEC 61000-4-2 Air-Gap Discharge. For more
information, send an e-mail to [email protected].
5
5 Page 
PRELIMINARY
XR19L400
REV. P1.0.0
SINGLE CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
FIGURE 6. XR19L400 TRANSMITTER AND RECEIVER
UART
Charge Pump
TX TX+
TX-
RX
RX+
RX-
RS-422/485
Transceiver
2.10 Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 64 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X/8X internal
clock. A bit time is 16 (8) clock periods (see EMSR bit-7). The transmitter sends the start-bit followed by the
number of data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and
TSR are reported in the Line Status Register (LSR bit-5 and bit-6).
2.10.1 Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
2.10.2 Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
11
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