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PDF XR19L212 Data sheet ( Hoja de datos )
| Número de pieza | XR19L212 | |
| Descripción | TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER | |
| Fabricantes | Exar Corporation | |
| Logotipo |  |
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XR19L212
TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
MAY 2007
REV. 1.0.0
GENERAL DESCRIPTION
The XR19L212 (L212) is a highly integrated device that
combines a full-featured two channel Universal
Asynchronous Receiver and Transmitter (UART) and RS-
232 transceivers. The L212 is designed to operate with a
single 3.3V or 5V power supply. The L212 is fully compliant
with EIA/TIA-232-F Standards from a +3.3V to +5.5V power
supply. The device operates at 1 Mbps data rate with worst
case 3K ohms load. Both RS-232 driver outputs and
receiver inputs can operate in harsh electrical environments
of +/-15V without damage and can survive multiple +/-15kV
ESD on the RS-232 lines, while maintaining RS-232 output
levels.
The L212 operates in four different modes: Active, Partial
Sleep, Full Sleep and Power-Save. Each mode can be
invoked via hardware or software. Upon power-up, the
L212 is in the Active mode where the UART and RS-232
transceiver function normally. In the Partial Sleep mode, the
internal crystal oscillator of the UART or charge pump of the
RS-232 transceiver is turned off. In Full Sleep mode, both
the crystal oscillator and the charge pump are turned off.
While the UART is in the Sleep mode, the Power-Save
mode isolates the core logic from the control signals (chip
select, read/write strobes, address and data bus lines) to
minimize the power consumption. The RS-232 receivers
remain active in any of these four modes.
APPLICATIONS
• Battery-Powered Equipment
• Handheld and Mobile Devices
• Handheld Terminals
• Industrial Peripheral Interfaces
• Point-of-Sale (POS) Systems
FEATURES
• Meets true EIA/TIA-232-F Standards from +3.3V to +5.5V
operation
• Up to 1 Mbps data transmission rate
• 45us sleep mode exit (charge pump to full power)
• ESD protection for RS-232 I/O pins at
■ +/-15kV - Human Body Model
■ +/-15kV - IEC 61000-4-2, Air-Gap Discharge
■ +/- 8kV - IEC 61000-4-2, Contact Discharge
• Software compatible with industry standard 16550 UART
• Intel/Motorola bus select
• Complete modem interface
• Sleep and Power-save modes to conserve battery power
• Wake-up interrupt upon exiting low power modes
FIGURE 1. BLOCK DIAGRAM
PwrSave
A2:A0
D7:D0
IOR#
IOW# (R/W#)
CSA# (CS#)
CSB#
INTA (IRQ#)
INTB
RESET (RESET#)
I/M#
RXBSEL
*5 V Tolerant
Inputs
Crystal
Osc/Buffer
BRG
64 Byte
TX & RX
FIFO
Modem
I/Os
TXA
RXA
RTSA#
CTSA#
Channel A
Channel B
UART
XR19L212
CTSB#
RTSB#
TXB
RXB
Charge Pump
5K
5K
VREF+
VREF-
TXDA
RXDA
RTSA
CTSA
Ch A Transceiver
Channel B
Transceiver
(See Figure 6)
RS-232 Transceiver
CTSB
RTSB
TXDB
TXB
RXDB
RXB
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
REV. 1.0.0
Pin Descriptions
XR19L212
TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
NAME
48-QFN
PIN#
TYPE
DESCRIPTION
I/M# 23 I Intel or Motorola Bus Select.
When I/M# pin is HIGH, 16 or Intel Mode, the device will operate in the Intel bus type of
interface.
When I/M# pin is LOW, 68 or Motorola mode, the device will operate in the Motorola bus
type of interface.
RESET
(RESET#)
35
I When I/M# pin is HIGH for Intel bus interface, this input becomes RESET (active high).
When I/M# pin is LOW for Motorola bus interface, this input becomes RESET# (active low).
A 40 ns minimum active pulse on this pin will reset the internal registers and all outputs of
the UART. The UART transmitter output will be held HIGH, the receiver input will be ignored
and outputs are reset during reset period (see Table 16).
C2P
C2N
36 - Charge pump capacitors. As shown in Figure 1, a 0.1 uF capacitor should be placed
34 between these 2 pins.
C1P
C1N
39 - Charge pump capacitors. As shown in Figure 1, a 0.1 uF capacitor should be placed
38 between these 2 pins.
VREFP
40 Pwr +5.0V generated by the charge pump.
VREFN
21 Pwr -5.0V generated by the charge pump.
R_EN 19 I When the supply voltage is < 3.6V, connect R_EN to GND.
When the supply voltage is > 3.6V, connect R_EN to VCC.
C3 42 I When the supply voltage is 3.3 V, C3A and C3B should be connected to VCC.
When the supply voltage is 5 V, C3A should be connected to C3B with a 1 uF capacitor to
GND.
RXBSEL
7
I When RXBSEL is HIGH, RXB is the input to the receiver of the UART.
When RXBSEL is LOW, RXDB is the input to the receiver of the UART.
FAST 15 I When FAST is HIGH, the maximum serial data rate is 1 Mbps.
When FAST is LOW, the maximum serial data rate is 250 Kbps.
VCC
37, 41 Pwr 3.3V to 5.5V power supply. All CMOS/TTL input pins, except XTAL1, are 5V tolerant.
GND 1, 17, 26 Pwr Power supply common, ground.
- PAD Pwr The center pad on the backside of the 48-QFN package is metallic and is not electrically
connected to anything inside the device. It must be soldered on to the PCB and may be
optionally connected to GND on the PCB. The thermal pad size on the PCB should be the
approximate size of this center pad and should be solder mask defined. The solder mask
opening should be at least 0.0025" inwards from the edge of the PCB thermal pad.
NOTE: Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain. For CMOS/TTL Voltage levels, ’LOW’
indicates a voltage in the range 0V to VIL and ’HIGH" indicates a voltage in the range VIH to VCC. For RS-232
Voltage levels, ’LOW’ is any voltage < 1.5V and ’HIGH’ is any voltage > 3V.
5
5 Page 
XR19L212
REV. 1.0.0
TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
The closest divisor that is obtainable in the L212 can be calculated using the following formula:
ROUND( (Required Divisor - TRUNC(Required Divisor) )*16)/16 + TRUNC(Required Divisor), where
DLM = TRUNC(Required Divisor) >> 8
DLL = TRUNC(Required Divisor) & 0xFF
DLD = ROUND( (Required Divisor-TRUNC(Required Divisor) )*16)
In the formulas above, please note that:
TRUNC (N) = Integer Part of N. For example, TRUNC (5.6) = 5.
ROUND (N) = N rounded towards the closest integer. For example, ROUND (7.3) = 7 and ROUND (9.9) = 10.
A >> B indicates right shifting the value ’A’ by ’B’ number of bits. For example, 0x78A3 >> 8 = 0x0078.
FIGURE 5. BAUD RATE GENERATOR
To Other
Channel
XTAL1
XTAL2
Crystal
Osc/
Buffer
Prescaler
Divide by 1
Prescaler
Divide by 4
DLL, DLM and DLD
Registers
MCR Bit-7=0
(default)
Fractional Baud
Rate Generator
Logic
16X or 8X
Sampling
Rate Clock
to Transmitter
and Receiver
MCR Bit-7=1
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet XR19L212.PDF ] | |
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