PDF XR16V798 Data sheet ( Hoja de datos )

Número de pieza	XR16V798
Descripción	HIGH PERFORMANCE 2.25V TO 3.6V OCTAL UART
Fabricantes	Exar Corporation
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No Preview Available ! xrwww.DataSheet4U.com XR16V798 HIGH PERFORMANCE 2.25V TO 3.6V OCTAL UART WITH FRACTIONAL BAUD RATE JANUARY 2006 GENERAL DESCRIPTION FEATURES REV. 1.0.0 The XR16V7981 (798), is a 2.25V to 3.6V octal Universal Asynchronous Receiver and Transmitter (UART) with 5V tolerant serial (modem) inputs. The highly integrated device is designed for high bandwidth requirement in communication systems. The global interrupt source register provides a complete interrupt status indication for all 8 channels to speed up interrupt parsing. Each UART has its own 16C550 compatible set of configuration registers, TX and RX FIFOs of 64 bytes, fully programmable transmit and receive FIFO trigger levels, TX and RX FIFO level counters, automatic RTS/CTS or DTR/ DSR hardware flow control with programmable hysteresis, autoamtic software (Xon/Xoff) flow control, RS-485 half-duplex direction control with programmable turn-around delay, Intel or Motorola bus interface and sleep mode with a wake-up indicator. NOTE: Covered by US patents #5,649,122 and #5,949,787 APPLICATIONS • Remote Access Servers • Ethernet Network to Serial Ports • Network Management • Factory Automation and Process Control • Point-of-Sale Systems • Multi-port RS-232/RS-422/RS-485 Cards • 2.25V to 3.6V with 5V Tolerant Serial Inputs • Single Interrupt output for all 8 UARTs • A Global Interrupt Source Register for all 8 UARTs • 5G “Flat” UART Registers for easier programming • Simultaneous Initialization of all UART channels • A General Purpose Command-driven 16-bit Timer/counter • Sleep Mode with Wake-up Indication • Highly Integrated Device for Space Saving • Each UART is independently controlled with: ■ 16C550 Compatible 5G Register Set ■ 64-byte Transmit and Receive FIFOs ■ Fractional Baud Rate Generator ■ Transmit and Receive FIFO Level Counters ■ Programmable TX and RX FIFO Trigger Level ■ Automatic RTS/CTS or DTR/DSR Flow Control ■ Automatic Xon/Xoff Software Flow Control ■ RS485 HDX Control Output with Selectable Turn-around Delay ■ Infrared (IrDA 1.0) Data Encoder/Decoder ■ Programmable Data Rate with Prescaler • Up to 8 Mbps Serial Data Rate • Pin compatible to XR16L788. Same 100-pin QFP Package (14x20x3 mm) FIGURE 1. BLOCK DIAGRAM RST# A7:A0 D7:D0 IOR# IOW# CS# INT# 16/68# Data Bus Interface Device Configuration Registers 16-bit Timer/Counter UART Channel 0 UART Regs BRG 64 Byte TX FIFO TX & RX IR ENDEC 64 Byte RX FIFO UART Channel 1 UART Channel 2 UART Channel 3 UART Channel 4 UART Channel 5 UART Channel 6 UART Channel 7 Crystal Osc/Buffer TX0, RX0, DTR0#, DSR0#, RTS0#, CTS0#, CD0#, RI0# TX7, RX7, DTR7#, DSR7#, RTS7#, CTS7#, CD7#, RI7# XTAL1 XTAL2 TMRCK Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com 1 page xr XR16V798 REV. 1.0.0 HIGH PERFORMANCE 2.25V TO 3.6V OCTAL UART WITH FRACTIONAL BAUD RATE NAME RX4 RTS4# CTS4# DTR4# DSR4# CD4# RI4# TX5 RX5 RTS5# CTS5# DTR5# DSR5# CD5# RI5# TX6 RX6 RTS6# CTS6# DTR6# DSR6# CD6# RI6# TX7 RX7 PIN # 57 62 58 63 59 60 61 56 49 54 50 55 51 52 53 46 39 44 40 45 41 42 43 38 31 TYPE DESCRIPTION I UART channel 4 Receive Data or infrared receive data. Normal RXD input idles HIGH. The infrared pulse can be inverted internally prior to decoding by setting FCTR bit-4. O UART channel 4 Request to Send or general purpose output (active LOW). See description of RTS0# pin. I UART channel 4 Clear to Send or general purpose input (active LOW). See descrip- tion of CTS0# pin. O UART channel 4 Data Terminal Ready or general purpose output (active LOW). See description of DTR0# pin. I UART channel 4 Data Set Ready or general purpose input (active LOW). See description of DSR0# pin. I UART channel 4 Carrier Detect or general purpose input (active LOW). I UART channel 4 Ring Indicator or general purpose input (active LOW). O UART channel 5 Transmit Data or infrared transmit data. I UART channel 5 Receive Data or infrared receive data. Normal RXD input idles HIGH. The infrared pulse can be inverted internally prior to decoding by setting FCTR bit-4. O UART channel 5 Request to Send or general purpose output (active LOW). See description of RTS0# pin. I UART channel 5 Clear to Send or general purpose input (active LOW). See descrip- tion of CTS0# pin. O UART channel 5 Data Terminal Ready or general purpose output (active LOW). See description of DTR0# pin. I UART channel 5 Data Set Ready or general purpose input (active LOW). See description of DSR0# pin. I UART channel 5 Carrier Detect or general purpose input (active LOW). I UART channel 5 Ring Indicator or general purpose input (active LOW). O UART channel 6 Transmit Data or infrared transmit data. I UART channel 6 Receive Data or infrared receive data. Normal RXD input idles HIGH. The infrared pulse can be inverted internally prior to decoding by setting FCTR bit-4. O UART channel 6 Request to Send or general purpose output (active LOW). See description of RTS0# pin. I UART channel 6 Clear to Send or general purpose input (active LOW). See descrip- tion of CTS0# pin. O UART channel 6 Data Terminal Ready or general purpose output (active LOW). See description of DTR0# pin. I UART channel 6 Data Set Ready or general purpose input (active LOW). See description of DSR0# pin. I UART channel 6 Carrier Detect or general purpose input (active LOW). I UART channel 6 Ring Indicator or general purpose input (active LOW). O UART channel 7 Transmit Data or infrared transmit data. I UART channel 7 Receive Data or infrared receive data. Normal RXD input idles HIGH. The infrared pulse can be inverted internally prior to decoding by setting FCTR bit-4. 5 5 Page xr XR16V798 REV. 1.0.0 HIGH PERFORMANCE 2.25V TO 3.6V OCTAL UART WITH FRACTIONAL BAUD RATE 2.7.1 Transmit Holding Register (THR) - Write Only The transmit holding register is an 8-bit register providing a data interface to the host processor. The host writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits, parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. Every time a write operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data location. 2.7.2 Transmitter Operation in non-FIFO Mode The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty. FIGURE 5. TRANSMITTER OPERATION IN NON-FIFO MODE Data Byte Transmit Holding Register (THR) THR Interrupt (ISR bit-1) Enabled by IER bit-1 16X or 8X Clock Transmit Shift Register (TSR) ML SS BB TXNOFIFO1 2.7.3 Transmitter Operation in FIFO Mode The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit-5) is set whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the amount of data in the FIFO falls below its programmed trigger level. The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when TSR/FIFO becomes empty. FIGURE 6. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE Transmit Data Byte Auto CTS Flow Control (CTS# pin) Flow Control Characters (Xoff1/2 and Xon1/2 Reg. Auto Software Flow Control T ransm it FIFO THR Interrupt (ISR bit-1) falls below the programmed Trigger Level and then when becomes empty. FIFO is Enabled by FCR bit-0=1 16X or 8X Clock Transmit Data Shift Register (TSR) T XF IF O 1 11 11 Page

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