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PDF XR16V554D Data sheet ( Hoja de datos )
| Número de pieza | XR16V554D | |
| Descripción | 2.25V TO 3.6V QUAD UART | |
| Fabricantes | Exar Corporation | |
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XR16V554/554D
2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO
MAY 2007
REV. 1.0.1
GENERAL DESCRIPTION
The XR16V554 (V554) is a quad Universal
Asynchronous Receiver and Transmitter (UART) with
16 bytes of transmit and receive FIFOs, selectable
receive FIFO trigger levels and data rates of up to 4
Mbps at 3.3 V. Each UART has a set of registers that
provide the user with operating status and control,
receiver error indications, and modem serial interface
controls. An internal loopback capability allows
onboard diagnostics. The V554 is available in a 48-
pin QFN, 64-pin LQFP, 68-pin PLCC and 80-pin
LQFP packages. The 64-pin and 80-pin packages
only offer the 16 mode interface, but the 48- and 68-
pin packages offer an additional 68 mode interface
which allows easy integration with Motorola
processors. The XR16V554IV (64-pin) offers three
state interrupt output while the XR16V554DIV
provides continuous interrupt output. The XR16V554
is compatible with the industry standard ST16C554.
FEATURES
• Pin-to-pin compatible with ST16C454, ST16C554,
TI’s TL16C554A and Philip’s SC16C554B
• Intel or Motorola Data Bus Interface select
• Four independent UART channels
■ Register Set Compatible to 16C550
■ Data rates of up to 4 Mbps at 3.3 V and 3.125
Mbps at 2.5 V
■ 16 byte Transmit FIFO
■ 16 byte Receive FIFO with error tags
■ 4 Selectable RX FIFO Trigger Levels
■ Full modem interface
• 2.25V to 3.6V supply operation
• Crystal oscillator or external clock input
APPLICATIONS
• Portable Appliances
• Telecommunication Network Routers
• Ethernet Network Routers
• Cellular Data Devices
• Factory Automation and Process Controls
FIGURE 1. XR16V554 BLOCK DIAGRAM
A2:A0
D7:D0
IOR#
IOW#
CSA#
CSB#
CSC#
CSD#
INTA
INTB
INTC
INTD
TXRDY# A-D
RXRDY# A-D
Reset
16/68#
INTSEL
Data Bus
Interface
* 5 Volt Tolerant Inputs
( Except XTAL1input)
UART Channel A
UART 16 Byte TX FIFO
Regs
TX & RX
BRG
16 Byte RX FIFO
UART Channel B
(same as Channel A)
UART Channel C
(same as Channel A)
UART Channel D
(same as Channel A)
Crystal Osc / Buffer
2.25V to 3.6 V VCC
GND
TXA, RXA, DTRA#,
DSRA#, RTSA#, CTSA#,
CDA#, RIA#
TXB, RXB, DTRB#,
DSRB#, RTSB#, CTSB#,
CDB#, RIB#
TXC, RXC, DTRC#,
DSRC#, RTSC#, CTSC#,
CDC#, RIC#
TXD, RXD, DTRD#,
DSRD#, RTSD#, CTSD#,
CDD#, RID#
XTAL1
XTAL2
554 BLK
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
REV. 1.0.1
Pin Description
XR16V554/554D
2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO
NAME
48-QFN
PIN #
64-LQFP
PIN #
68-PLCC
PIN#
80-LQFP
PIN #
TYPE
DESCRIPTION
CSB#
(A3)
9
11 20 13 I When 16/68# pin is HIGH, this input is chip select B
(active low) to enable channel B in the device.
When 16/68# pin is LOW, this input becomes address
line A3 which is used for channel selection in the Motor-
ola bus interface.
CSC#
27
38
50
49 I When 16/68# pin is HIGH, this input is chip select C
(A4) (active low) to enable channel C in the device.
When 16/68# pin is LOW, this input becomes address
line A4 which is used for channel selection in the Motor-
ola bus interface.
CSD#
31
42
54
53 I When 16/68# pin is HIGH, this input is chip select D
(VCC)
(active low) to enable channel D in the device.
When 16/68# pin is LOW, this input is not used and
should be connected VCC.
INTA
(IRQ#)
4
6 15 8 O When 16/68# pin is HIGH for Intel bus interface, this
(OD) ouput becomes channel A interrupt output. The output
state is defined by the user and through the software
setting of MCR[3]. INTA is set to the active mode when
MCR[3] is set to a logic 1. INTA is set to the three state
mode when MCR[3] is set to a logic 0 (default). See
MCR[3].
When 16/68# pin is LOW for Motorola bus interface,
this output becomes device interrupt output (active low,
open drain). An external pull-up resistor is required for
proper operation.
INTB 10 12 21 14 O When 16/68# pin is HIGH for Intel bus interface, these
INTC 26 37 49 48
INTD 32 43 55 54
(N.C.)
ouputs become the interrupt outputs for channels B, C,
and D. The output state is defined by the user through
the software setting of MCR[3]. The interrupt outputs
are set to the active mode when MCR[3] is set to a logic
1 and are set to the three state mode when MCR[3] is
set to a logic 0 (default). See MCR[3].
When 16/68# pin is LOW for Motorola bus interface,
these outputs are unused and will stay at logic zero
level. Leave these outputs unconnected.
TXRDY#
-
- 39 35 O Transmitter Ready (active low). This output is a logi-
cally ANDed status of TXRDY# A-D. See Table 5. If this
output is unused, leave it unconnected.
RXRDY#
-
- 38 34 O Receiver Ready (active low). This output is a logically
ANDed status of RXRDY# A-D. See Table 5. If this out-
put is unused, leave it unconnected.
5
5 Page 
XR16V554/554D
REV. 1.0.1
2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO
2.2 Device Reset
The RESET input resets the internal registers and the serial interface outputs in all channels to their default
state (see Table 13). An active high pulse of longer than 40 ns duration will be required to activate the reset
function in the device. Following a power-on reset or an external reset, the V554 is software compatible with
previous generation of UARTs, 16C454 and 16C554.
2.3 Channel Selection
The UART provides the user with the capability to bi-directionally transfer information between an external
CPU and an external serial communication device. During Intel Bus Mode (16/68# pin is connected to VCC), a
logic 0 on chip select pins, CSA#, CSB#, CSC# or CSD# allows the user to select UART channel A, B, C or D
to configure, send transmit data and/or unload receive data to/from the UART. Selecting all four UARTs can be
useful during power up initialization to write to the same internal registers, but do not attempt to read from all
four uarts simultaneously. Individual channel select functions are shown in Table 1.
TABLE 1: CHANNEL A-D SELECT IN 16 MODE
CSA# CSB# CSC# CSD#
FUNCTION
1111
UART de-selected
0111
Channel A selected
1011
Channel B selected
1101
Channel C selected
1110
Channel D selected
0000
Channels A-D selected
During Motorola Bus Mode (16/68# pin is connected to GND), the package interface pins are configured for
connection with Motorola, and other popular microprocessor bus types. In this mode the V554 decodes two
additional addresses, A3 and A4, to select one of the four UART ports. The A3 and A4 address decode
function is used only when in the Motorola Bus Mode. See Table 2.
TABLE 2: CHANNEL A-D SELECT IN 68 MODE
CS# A4 A3
FUNCTION
1XX
UART de-selected
000
Channel A selected
001
Channel B selected
010
Channel C selected
011
Channel D selected
11
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| PDF Descargar | [ Datasheet XR16V554D.PDF ] | |
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