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PDF XR16L580 Data sheet ( Hoja de datos )
| Número de pieza | XR16L580 | |
| Descripción | SMALLEST 2.25V TO 5.5V UART | |
| Fabricantes | Exar Corporation | |
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XR16L580
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
JANUARY 2004
GENERAL DESCRIPTION
FEATURES
REV. 1.2.0
The XR16L580 (L580) is a 2.25 to 5.5 volt Universal
Asynchronous Receiver and Transmitter (UART) with
5 volt tolerant inputs and a reduced pin count. It is
pin-to-pin and software compatible to industry
standard 16C450, 16C550, ST16C580, ST16C650A
and XR16C850 UARTs. It has 16 bytes of TX and RX
FIFOs and is capable of operating up to serial data
rate of 1 Mbps at 2.25 volt supply voltage. The
internal registers is compatible to the 16C550
register set plus enhanced registers for additional
features to support today’s high bandwidth data
communication needs. The enhanced features
include Intel or Motorola data bus interface to match
your CPU interface, automatic hardware and
software flow control to prevent data loss, selectable
RX and TX trigger levels for more efficient interrupt
service, wireless infrared (IrDA) encoder/decoder for
wireless applications and a unique Power-Save mode
to increase battery operating time. The device comes
in the 48-TQFP and a very small 32-QFN packages in
industrial temperature range.
APPLICATIONS
• Handheld Terminals and Tablets
• Handheld Computers
• Wireless Portable Point-of-Sale Terminals
• Cellular Phones DataPort
• GPS Devices
• Personal Digital Assistants Modules
• Battery Operated Instruments
• Industry Smallest Full Featured UART
• 2.25V to 5.5V Operation
• 5V Tolerant Inputs
• Intel/Motorola Bus Select
• ’0 ns’ Address Hold Time (TAH and TADH)
• Pin and Software Compatible to industry standard
16C450, 16C550, ST16C580, ST16C650A and
XR16C850 in the 48-TQFP package.
• 16-byte Transmit FIFO
• 16-byte Receive FIFO with Errors Flags
• Selectable RX and TX FIFO Trigger Levels
• Automatic Hardware (RTS/CTS) Flow Control
• Automatic Software (Xon/Xoff) Flow Control
• Up to 3.125 Mbps Data Rate at 5V and 2 Mbps at
3.3V and 1 Mbps at 2.25V Operation with External
Clock Input
• Infrared (IrDA) Encoder/Decoder
• Complete Modem Interface
• Power-Save Mode to conserve battery power
• Sleep Mode with Wake-up Interrupt
• Small 32-QFN (5x5x0.9mm) package
• Compatible to standard 48-TQFP packages
without the following redundant signals: IOR,
IOW, CS1, CS2, TXRDY#, RXRDY#, RCLK,
BAUDOUT#, OP1# and OP2#
• Industrial Temperature Grade(-40 to +85oC)
FIGURE 1. BLOCK DIAGRAM
PwrSave
A2:A0
D7:D0
IOR#
IOW# (R/W#)
CS#
INT (IRQ#)
RESET
(RESET#)
16/68#
Intel or
Motorola
Data Bus
Interface
*5 V Tolerant Inputs
UART
UART 16 Byte TX FIFO
Regs
TX
&
RX
IR
ENDEC
BRG 16 Byte RX FIFO
Crystal Osc/Buffer
VCC
(2.25 to 5.5 V)
GND
TX, RX,
RTS#, CTS#,
DTR#, DSR#,
RI#, CD#
XTAL1
XTAL2
GNugget_BLK
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
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áç
REV. 1.2.0
XR16L580
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
1.0 PRODUCT DESCRIPTION
The XR16L580 (L580) is an enhanced 16C550 Universal Asynchronous Receiver and Transmitter (UART). Its
features set is compatible to the ST16C580 device and additionally offers Intel or Motorola data bus interface
and Power-Save to isolate the data bus interface during Sleep mode. Hence, the L580 adds 2 more inputs: 16/
68# and PwrSave pins. The XR16L580 can operate from 2.25V to 5.5V with 5 volt tolerant inputs. The
configuration registers set is 16550 UART compatible for control, status and data transfer. Also, the L580 has
16-bytes of transmit and receive FIFOs, automatic RTS/CTS hardware flow control, automatic Xon/Xoff and
special character software flow control, transmit and receive FIFO trigger levels, infrared encoder and decoder
(IrDA ver 1.0), programmable baud rate generator with a prescaler of divide by 1 or 4. The L580 is fabricated
using an advanced CMOS process.
Enhanced Features
The L580 UART provides a solution that supports 16 bytes of transmit and receive FIFO memory. The L580 is
designed to work with low supply voltage and high performance data communication systems, that require fast
data processing time. Increased performance is realized in the L580 by the transmit and receive FIFOs, FIFO
trigger level controls and automatic flow control mechanism. This allows the external processor to handle more
networking tasks within a given time. This increases the service interval giving the external CPU additional
time for other applications and reducing the overall UART interrupt servicing time. In addition, the L580
provides the Power-Save mode that drastically reduces the power consumption when the device is not used.
The combination of the above greatly reduces the CPU’s bandwidth requirement, increases performance, and
reduces power consumption.
Data Bus Interface, Intel or Motorola Type
The L580 provides a host interface that supports Intel or Motorola microprocessor (CPU) data bus interface.
The Intel bus compatible interface allows direct interconnect to Intel compatible type of CPUs using IOR#,
IOW# and CS# inputs for data bus operation. The Motorola bus compatible interface instead uses the R/W#
and CS# signals for data bus transactions. See pin description section for details on all the control signals. The
Intel and Motorola bus interface selection is made through the pin, 16/68#.
Data Rate
The L580 is capable of operation up to 3.125 Mbps at 5V, 2 Mbps at 3.3V and 1 Mbps at 2.5V supply with 16X
internal sampling clock rate. The device can operate with an external 24 MHz crystal on pins XTAL1 and
XTAL2, or external clock source of up to 50 MHz on XTAL1 pin. With a typical crystal of 14.7456 MHz, all
standard data rates of up to 921.6 kbps can be generated.
Internal Enhanced Register Sets
The L580 UART has a set of enhanced registers providing control and monitoring functions. Interrupt enable/
disable and status, FIFO enable/disable, selectable TX and RX FIFO trigger levels, automatic hardware/
software flow control enable/disable, programmable baud rates, infrared encoder/decoder enable/disable,
modem interface controls and status, sleep mode and Power-Save mode are all standard features. Following a
power on reset or an external reset (and operating in 16 or Intel Mode), the registers defaults to the reset
condition and its is compatible with previous generation of UARTs, 16C450, 16C550, 16C580, 16C650A and
16C850.
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REV. 1.2.0
XR16L580
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
2.10 Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal
clock. A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits,
inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in
the Line Status Register (LSR bit-5 and bit-6).
2.10.1 Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 16 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
2.10.2 Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE
Data
Byte
Transmit
Holding
Register
(THR)
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
16X Clock
Transmit Shift Register (TSR)
ML
SS
BB
TXNOFIFO1
2.10.3 Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 16 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
amount of data in the FIFO falls below its programmed trigger level. The transmit empty interrupt is enabled by
IER bit-1. The Transmitter Empty Flag (LSR bit-6) is set when both the TSR and the FIFO become empty.
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| Páginas | Total 47 Páginas | |
| PDF Descargar | [ Datasheet XR16L580.PDF ] | |
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