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PDF XR16L2552 Data sheet ( Hoja de datos )
| Número de pieza | XR16L2552 | |
| Descripción | 2.25V TO 5.5V DUART | |
| Fabricantes | Exar Corporation | |
| Logotipo |  |
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xrwww.DataSheet4U.com
MAY 2005
GENERAL DESCRIPTION
The XR16L2552 (L2552) is a dual universal
asynchronous receiver and transmitter (UART) with 5
volt tolerant inputs. The XR16L2552 is an improved
version of the ST16C2552 UART with lower operating
voltages and 5 volt tolerant inputs. The L2552
provides enhanced UART functions with 16 byte TX
and RX FIFOs, automatic hardware (RTS/CTS) and
software (Xon/Xoff) flow control, and a complete
modem control interface. Onboard status registers
provide the user with error indications and
operational status. Indepedendent programmable
baud rate generators are provided to select transmit
and receive clock rates up to 3.125Mbps. An internal
loop-back capability allows onboard diagnostics. The
L2552 provides block mode data transfers (DMA)
through FIFO controls. DMA transfer monitoring is
provided through the signals TXRDY# and RXRDY#.
An Alternate Function Register provides the user with
the ability to write the control registers for both UARTs
concurrently and selection of the Multi-Function
output (Baudout#, OP2#, or RXRDY#).
NOTE: 1 Covered by U.S. Patent #5,649,122.
APPLICATIONS
• Portable Appliances
• Telecommunication Network Routers
• Ethernet Network Routers
• Cellular Data Devices
• Factory Automation and Process Controls
FIGURE 1. XR16L2552 BLOCK DIAGRAM
XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
FEATURES
REV. 1.1.1
• 2.25 to 5.5 Volt Operation
• 5 Volt Tolerant Inputs
• Pin-to-pin and functionally compatible to National
PC16552
• Pin-to-pin Compatible to Exar’s ST16C2552,
XR16L2752 and XR16C2852 in the 44-PLCC
• 2 Independent UART Channels
■ Up to 3.125Mbps with external clock of 50 MHz
■ Register Set Compatible to 16C550
■ 16 byte Transmit FIFO to reduce the bandwidth
requirement of the external CPU
■ 16 byte Receive FIFO with error tags to reduce
the bandwidth requirement of the external CPU
■ 4 selectable RX FIFO Trigger Levels
■ Automatic RTS/CTS hardware flow control
■ Automatic XonXoff software flow control
■ Wireless infrared encoder/decoder
■ Full Modem Interface (CTS#, RTS#, DSR#,
DTR#, RI#, CD#)
■ Programmable character lengths (5, 6, 7, 8)
with even, odd, or no parity
■ Multi-Function output allows more package
functions with fewer I/O pins
• Concurrent write to Channels A and B
• Crystal oscillator or external clock input
• 48-TQFP (7x7x1.0 mm) and 44-PLCC packages
A2:A0
D7:D0
IOR#
IOW#
CS#
CHSEL
INTA
INTB
TXRDY# A/B
RXRDY# A/B
(48-TQFP Only)
MFA#
(OP2A#,
BAUDOUTA#, or
RXRDYA#)
MFB#
(OP2B#,
BAUDOUTB#, or
RXRDYB#)
Reset
8-bit Data
Bus
Interface
* 5 Volt Tolerant Inputs
UART Channel A
UART
Regs
BRG
16 Byte TX FIFO
TX & RX
16 Byte RX FIFO
UART Channel B
(same as Channel A)
Crystal Osc/Buffer
Modem Control Logic
2.25 to 5.5 Volt VCC
GND
TXA
RXA
TXB
RXB
XTAL1
XTAL2
CTS#A/B, RI#A/B,
CD#A/B, DSR#A/B
DTR#A/B, RTS#A/B
2552BLK
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
xr
REV. 1.1.1
XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
Pin Description
NAME
48-TQFP
PIN#
44-PLCC
PIN #
TYPE
DESCRIPTION
RIB# 27 31 I UART channel B Ring-Indicator (active low) or general purpose input. This
input should be connected to VCC when not used. This input has no effect on
the UART.
MFA#
32
35 O Multi-Function Output Channel A. This output pin can function as the OP2A#,
BAUDOUTA#, or RXRDYA# pin. One of these output signal functions can be
selected by the user programmable bits 1-2 of the Alternate Function Register
(AFR). These signal functions are described as follows:
1) OP2A# - When OP2A# (active low) is selected, the MF# pin is a logic 0
when MCR bit-3 is set to a logic 1 (see MCR bit-3). MCR bit-3 defaults to a
logic 1 condition after a reset or power-up.
2) BAUDOUTA# - When BAUDOUTA# function is selected, the 16X Baud rate
clock output is available at this pin.
3) RXRDYA# - RXRDYA# (active low) is intended for monitoring DMA data
transfers. If using the 48-TQFP package, this output is already available at pin
31.
MFB#
14
If it is not used, leave it unconnected.
19 O Multi-Function Output ChannelB. This output pin can function as the OP2B#,
BAUDOUTB#, or RXRDYB# pin. One of these output signal functions can be
selected by the user programmable bits 1-2 of the Alternate Function Register
(AFR). These signal functions are described as follows:
1) OP2B# - When OP2B# (active low) is selected, the MF# pin is a logic 0
when MCR bit-3 is set to a logic 1 (see MCR bit-3). MCR bit-3 defaults to a
logic 1 condition after a reset or power-up.
2) BAUDOUTB# - When BAUDOUTB# function is selected, the 16X Baud rate
clock output is available at this pin.
3) RXRDYB# - RXRDYB# (active low) is intended for monitoring DMA data
transfers. If using the 48-TQFP package, this output is already available at pin
8.
ANCILLARY SIGNALS
XTAL1
5
XTAL2
7
RESET
16
11
13
21
VCC
GND
29, 42
6, 17
44, 33
22, 12
If it is not used, leave it unconnected.
I Crystal or external clock input.
O Crystal or buffered clock output.
I Reset (active high) - A longer than 40 ns logic 1 pulse on this pin will reset the
internal registers and all outputs. The UART transmitter output will be held at
logic 1, the receiver input will be ignored and outputs are reset during reset
period (see External Reset Conditions).
Pwr 2.25V to 5.5V power supply. All input pins are 5V tolerant.
Pwr Power supply common, ground.
5
5 Page 
xr
REV. 1.1.1
XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
To obtain maximum data rate, it is necessary to use full rail swing on the clock input. See external clock
operating frequency over power supply voltage chart in Figure 6.
FIGURE 6. OPERATING FREQUENCY CHART. REQUIRES A 2K OHMS PULL-UP RESIS-
TOR ON XTAL2 PIN TO INCREASE OPERATING SPEED
Operating frequency for XR16L2552
with external clock and a 2K ohms
pull-up resistor on XTAL2 pin.
80
-40oC
70 25oC
85oC
60
50
40
30
3.0 3.5 4.0 4.5 5.0 5.5
Suppy Voltage
The L2552 divides the basic external clock by 16. The basic 16X clock provides table rates to support standard
and custom applications using the same system design. The Baud Rate Generator divides this 16X clock by
any divisor from 1 to 216 -1. The rate table is configured via the DLL and DLM internal register functions.
Customized Baud Rates can be achieved by selecting the proper divisor values for the MSB and LSB sections
of baud rate generator.
Table 5 shows the standard data rates available with a 14.7456 MHz crystal or external clock at 16X sampling
rate. When using a non-standard frequency crystal or external clock, the divisor value can be calculated for
DLL/DLM with the following equation.
divisor (decimal) = (XTAL1 or External clock frequency ) / (serial data rate x 16)
TABLE 5: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK
OUTPUT Data Rate DIVISOR FOR 16x DIVISOR FOR 16x
MCR Bit-7=0
Clock (Decimal) Clock (HEX)
DLM PROGRAM
VALUE (HEX)
DLL PROGRAM
VALUE (HEX)
DATA RATE
ERROR (%)
400
2304
900
09
00 0
2400
384 180
01
80 0
4800 192 C0 00 C0 0
9600
96
60
00
60 0
19.2k
48
30
00
30 0
38.4k
24
18
00
18 0
76.8k
12
0C
00
0C 0
11
11 Page | ||
| Páginas | Total 47 Páginas | |
| PDF Descargar | [ Datasheet XR16L2552.PDF ] | |
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