|
|
PDF XR16L2551 Data sheet ( Hoja de datos )
| Número de pieza | XR16L2551 | |
| Descripción | LOW VOLTAGE DUART | |
| Fabricantes | Exar Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de XR16L2551 (archivo pdf) en la parte inferior de esta página. Total 48 Páginas | ||
|
No Preview Available !
áçwww.DataSheet4U.com
SEPTEMBER 2003
GENERAGENERAL DESCRIPTION
The XR16L2551 (L2551) is a low voltage dual
universal asynchronous receiver and transmitter
(UART) with 5 Volt tolerant inputs. The device
includes additional capability over the ST16C2550:
Intel and Motorola data bus interface selection,
hardware and software flow control, infrared encoder/
decoder, sleep mode and a PowerSave mode for
battery operation. The L2551’s enhanced register set
is compatible to the ST16C2550 and XR16L2550. It
supports the Exar’s enhanced features of 16 bytes of
TX and RX FIFOs and a complete modem interface.
Onboard registers provide the user with operational
status and data error tags. An internal loopback
capability allows onboard diagnostics. Independent
programmable baud rate generator is provided in
each channel to support data rates up to 3.125 Mbps.
NOTE: 1 Covered by U.S. Patent #5,649,122.
APPLICATIONS
• Battery Operated Instruments
• Data Port Adapters
• Handheld Appliances
• Radio Frequency Data Modems
• Base Stations
• USB Hubs
• Industrial Automation Controls
XR16L2551
LOW VOLTAGE DUART WITH POWERSAVE
FEATURES
REV. 1.0.0
• 2.25 to 5.5 Volt Operation
• 5 Volt Tolerant Inputs
• Intel or Motorola Bus Interface Select (16/68#)
pin
• Pin-to-pin compatible to XR16L2751CM
• Two Independent UARTs
s Up to 3.125 Mbps at 5V, 2 Mbps at 3.3V, and 1
Mbps at 2.5V with external clock input
s Up to 1.5 Mbps at 5V, 1.25 Mbps at 3.3V and 1
Mbps at 2.5V with crystal clock input
s 16 bytes of Transmit and Receive FIFOs
s Automatic RTS/CTS hardware flow control
s Automatic Xon/Xoff software flow control
s Wireless infrared encoder/decoder
s Receive FIFO trigger levels select
s Programmable character lengths (5, 6, 7 or 8)
with even, odd, forced or no parity
s Full Modem Interface (CTS#, RTS#, DSR#,
DTR#, RI#, CD#) in the 48-TQFP package
• Sleep Mode with PowerSave feature for battery
operation
• Industrial Temperature range
• Tiny 32-QFN, no lead package (5x5x0.9mm)
• 48-TQFP Package
FIGURE 1. XR16L2551 BLOCK DIAGRAM
PwrSave
A2:A0
D7:D0
IOR# (VCC)
IOW# (R/W#)
CSA# (CS#)
CSB# (A3)
INTA (IRQ#)
INTB (logic 0)
TXRDYA#
TXRDYB#
RXRDYA#
RXRDYB#
Reset (Reset#)
16/68#
Intel or
Motorola
Data Bus
Interface
*5 Volt Tolerant Inputs
UART Channel A
UART
Regs
BRG
16 Byte TX FIFO
TX & RX IR
ENDEC
16 Byte RX FIFO
UART Channel B
(same as Channel A)
Crystal Osc/Buffer
2.25 to 5.5 Volt VCC
GND
TXA, RXA,
RTSA#, CTSA#,
( DTR#, DSR#
CD#, RIA#, OP2A# )
TXB, RXB,
RTSB#, CTSB#,
( DTRB#, DSRB#
CDB#, RIB#, OP2B# )
XTAL1
XTAL2
2551BLK
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
áç
REV. 1.0.0
Pin Description
NAME
32-QFN
PIN #
OP2A#
-
TXB
RXB
6
3
RTSB#
CTSB#
DTRB#
DSRB#
15
16
-
-
CDB#
-
RIB#
-
OP2B#
-
ANCILLARY SIGNALS
XTAL1
10
XTAL2
11
16/68#
17
XR16L2551
LOW VOLTAGE DUART WITH POWERSAVE
48-TQFP
PIN #
32
8
4
22
23
35
20
16
21
9
TYPE
DESCRIPTION
O Output Port 2 Channel A - The output state is defined by the user and
through the software setting of MCR[3]. INTA is set to the active mode
and OP2A# output to a logic 0 when MCR[3] is set to a logic 1. INTA is
set to the three state mode and OP2A# to a logic 1 when MCR[3] is set
to a logic 0. This output should not be used as a general output else it
will disturb the INTA output functionality. If it is not used at all, leave it
unconnected.
O UART channel B Transmit Data. If it is not used, leave it unconnected.
I UART channel B Receive Data. Normal receive data input must idle at
logic 1 condition. If it is not used, tie it to VCC or pull it high via a 100k
ohm resistor.
O UART channel B Request-to-Send (active low) or general purpose out-
put. If it is not used, leave it unconnected.
I UART channel B Clear-to-Send (active low) or general purpose input.
This input should be connected to VCC when not used.
O UART channel B Data-Terminal-Ready (active low) or general purpose
output. If it is not used, leave it unconnected.
I UART channel B Data-Set-Ready (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
I UART channel B Carrier-Detect (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
I UART channel B Ring-Indicator (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
O Output Port 2 Channel B - The output state is defined by the user and
through the software setting of MCR[3]. INTB is set to the active mode
and OP2B# output to a logic 0 when MCR[3] is set to a logic 1. INTB is
set to the three state mode and OP2B# to a logic 1 when MCR[3] is set
to a logic 0. This output should not be used as a general output else it
will disturb the INTB output functionality. If it is not used, leave it uncon-
nected.
13 I Crystal or external clock input.
14 O Crystal or buffered clock output.
24 I Intel or Motorola Bus Select.
When 16/68# pin is at logic 1, 16 or Intel Mode, the device will operate
in the Intel bus type of interface.
When 16/68# pin is at logic 0, 68 or Motorola mode, the device will
operate in the Motorola bus type of interface.
5
5 Page 
áç
REV. 1.0.0
XR16L2551
LOW VOLTAGE DUART WITH POWERSAVE
FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS
XTAL1
XTAL2
R2
500 KΩ - 1 MΩ
R1
0-120 Ω
(Optional)
C1
22-47 pF
Y1
1.8432 MHz
to
24 MHz
C2
22-47 pF
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100 ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 4), with an external 500 kΩ to
1 MΩ resistor across it. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal
baud rate generator for standard or custom rates. Typical oscillator connections are shown in Figure 4. For
further reading on oscillator circuit please see application note DAN108 on EXAR’s web site.
2.8 Programmable Baud Rate Generator
A single baud rate generator is provided for the transmitter and receiver, allowing independent TX/RX channel
control. The programmable Baud Rate Generator is capable of operating with a crystal frequency of up to 24
MHz. However, with an external clock input on XTAL1 pin and a 2K ohms pull-up resistor on XTAL2 pin (as
shown in Figure 5) it can extend its operation up to 64 MHz (4Mbps serial data rate) at room temperature and
5.0V.
FIGURE 5. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE
External Clock
vcc
gnd
VCC
R1
2K
XTAL1
XTAL2
11
11 Page | ||
| Páginas | Total 48 Páginas | |
| PDF Descargar | [ Datasheet XR16L2551.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| XR16L2550 | LOW VOLTAGE DUART | Exar Corporation |
| XR16L2551 | LOW VOLTAGE DUART | Exar Corporation |
| XR16L2552 | 2.25V TO 5.5V DUART | Exar Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |