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PDF PC33975 Data sheet ( Hoja de datos )
| Número de pieza | PC33975 | |
| Descripción | Multiple Switch Detection Interface | |
| Fabricantes | Freescale Semiconductor | |
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Technical Data
Document order number: MC33975
Rev 4.0, 08/2005
Multiple Switch Detection
Interface with Suppressed
Wake-Up and 32mA Wetting
Current
Freescale offers multiple Switch Detection Interface Devices. The
33975 Multiple Switch Detection Interface with Suppressed Wake-Up
is designed to detect the closing and opening of up to 22 switch
contacts. The switch status, either open or closed, is transferred to the
microprocessor unit (MCU) through a serial peripheral interface (SPI).
The device also features a 22-to-1 analog multiplexer for reading
inputs as analog.
33975
33975A
MULTIPLE SWITCH
DETECTION INTERFACE WITH
SUPPRESSED WAKE-UP
The 33975 device has two modes of operation, Normal and Sleep.
Normal mode allows programming of the device and supplies switch
contacts with pull-up or pull-down current as it monitors switch change
of state. The Sleep mode provides low quiescent current, which makes
the 33975 ideal for automotive and industrial products requiring low
sleep state currents.
Improvements are a programmable interrupt timer for Sleep mode
that can be disabled, switch detection currents of 32 mA and 4.0 mA
for switch-to-ground inputs, and an interrupt bit that can be reset.
EK Suffix (Pb-Free)
98ARL10543D
32-TERMINAL SOICW EP
Features
ORDERING INFORMATION
• Designed to Operate 5.5 V ≤ VPWR ≤ 28 V
• Switch Input Voltage Range -14 V to VPWR
• Interfaces Directly to Microprocessor Using 3.3 V/5.0 V SPI
Protocol
• Selectable Wake-Up on Change of State
Device
MC33975EK/R2
PC33975AEK/R2
Temperature
Range (TA)
-40°C to 125°C
Package
32 SOICW-EP
• Selectable Wetting Current (32 mA or 4.0 mA for switch-to-ground
inputs)
• 8 Programmable Inputs (Switches to Battery or Ground)
• 14 Switch-to-Ground Inputs
• VPWR Standby Current 100 µA Typical, VDD Standby Current 20 µA Typical
• Pb-free 32-terminal suffix EK
VDD
VBAT
VBAT
VBAT
33975
SP0 VPWR
SP1
VDD
SP7
SG0
SG1
SG12
WAKE
SI
SCLK
CS
SO
INT
AMUX
VDD
Power Supply
LVI
Enable
Watchdog
Reset
MCU
MOSI
SCLK
CS
MISO
INT
AN0
SG13
GND
Figure 1. 33975 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
1 page  
MAXIMUM RATINGS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these limits may cause malfunction or permanent
damage to the device.
Rating
Symbol
Value
Unit
ELECTRICAL RATINGS
VDD Supply Voltage
CS, SI, SO, SCLK, INT, AMUX
WAKE
VPWR Supply Voltage
Switch Input Voltage Range
MC33975
PC339775A
Frequency of SPI Operation (VDD = 5.0 V)
ESD Voltage (1)
Human Body Model (2)
Applies to all non-input terminals
Machine Model
Charge Device Model
Corner Terminals
Interior Terminals
–
–
–
–
–
–
VESD
-0.3 to 7.0
-0.3 to 7.0
-0.3 to 40
-0.3 to 50
-14 to 38
-14 to 40
6.0
±4000
±2500
±200
750
500
VDC
VDC
VDC
VDC
VDC
MHz
V
THERMAL RATINGS
Operating Temperature
Ambient
Junction
Case
Storage Temperature
Power Dissipation (3)
Thermal Resistance
Junction to Ambient
Between the Die and the Exposed Die Pad (4)
TA
TJ
TC
TSTG
PD
RθJA
RθJC
-40 to 125
-40 to 150
-40 to 125
-55 to 150
1.7
71
1.2
°C
°C
W
°C/W
Peak Package Reflow Temperature During Solder Mounting (5)
TSOLDER
245
°C
Notes
1. ESD testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), the Machine Model (CZAP = 200
pF, RZAP = 0 Ω), and the Charge Device Model.
2. All Programmable Switches (SP) and Switch-to-Ground (SG) input terminals when tested individually.
3. Maximum power dissipation at TJ =150°C junction temperature with no heatsink used.
4. Thermal resistance between the die and the exposed die pad.
5. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits
may cause malfunction or permanent damage to the device.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33975
5
5 Page 
FUNCTIONAL DESCRIPTIONS
INTRODUCTION
FUNCTIONAL DESCRIPTIONS
INTRODUCTION
The 33975 device is an integrated circuit designed to
provide systems with ultra-low quiescent sleep/wake-up
modes and a robust interface between switch contacts and a
microprocessor. The 33975 replaces many of the discrete
components required when interfacing to microprocessor-
based systems while providing switch ground offset
protection, contact wetting current, and system wake-up.
The 33975 features 8-programmable switch-to-ground or
switch-to-battery inputs and 14 switch-to-ground inputs. All
switch inputs may be read as analog inputs through the
analog multiplexer (AMUX). Other features include a
programmable wake-up timer, programmable interrupt timer,
programmable wake-up/interrupt bits, and programmable
wetting current settings.
This device is designed primarily for automotive
applications but may be used in a variety of other applications
such as computer, telecommunications, and industrial
controls.
FUNCTIONAL TERMINAL DESCRIPTION
CHIP SELECT (CS)
The system MCU selects the 33975 to receive
communication using the chip select (CS) terminal. With the
CS in a logic low state, command words may be sent to the
33975 via the serial input (SI) terminal, and switch status
information can be received by the MCU via the serial output
(SO) terminal. The falling edge of CS enables the SO output,
latches the state of the INT terminal, and the state of the
external switch inputs.
Rising edge of the CS initiates the following operation:
1. Disables the SO driver (high impedance)
1. INT terminal is reset to logic [1], except when additional
switch changes occur during CS low (see Figure 6,
page 10).
1. Activates the received command word, allowing the
33975 to act upon new data from switch inputs.
To avoid any spurious data, it is essential the high-to-low
and low-to-high transitions of the CS signal occur only when
SCLK is in a logic low state. Internal to the 33975 device is an
active pull-up to VDD on CS.
In Sleep mode the negative edge of CS (VDD applied) will
wake up the 33975 device. Data received from the device
during CS wake-up may not be accurate.
SERIAL CLOCK (SCLK)
The system clock (SCLK) terminal clocks the internal shift
register of the 33975. The SI data is latched into the input
shift register on the falling edge of SCLK signal. The SO
terminal shifts the switch status bits out on the rising edge of
SCLK. The SO data is available for the MCU to read on the
falling edge of SCLK. False clocking of the shift register must
be avoided to ensure validity of data. It is essential the SCLK
terminal be in a logic low state whenever CS makes any
transition. For this reason, it is recommended, though not
necessary, that the SCLK terminal is commanded to a low
logic state as long as the device is not accessed and CS is in
a logic high state. When the CS is in a logic high state, any
signal on the SCLK and SI terminals will be ignored and the
SO terminal is tri-state.
SERIAL INPUT (SI)
The SI terminal is used for serial instruction data input. SI
information is latched into the input register on the falling
edge of SCLK. A logic high state present on SI will program
a one in the command word on the rising edge of the CS
signal. To program a complete word, 24 bits of information
must be entered into the device.
SERIAL OUTPUT (SO)
The SO terminal is the output from the shift register. The
SO terminal remains tri-stated until the CS terminal
transitions to a logic low state. All open switches are reported
as zero, all closed switches are reported as one. The
negative transition of CS enables the SO driver.
The first positive transition of SCLK will make the status
data bit 24 available on the SO terminal. Each successive
positive clock will make the next status data bit available for
the MCU to read on the falling edge of SCLK. The SI/SO
shifting of the data follows a first-in-first-out protocol, with
both input and output words transferring the most significant
bit (MSB) first.
INTERRUPT OUTPUT (INT)
The INT terminal is an interrupt output from the 33975
device. The INT terminal is an open-drain output with an
internal pull-up to VDD. In Normal mode, a switch state
change will trigger the INT terminal (when enabled). The INT
terminal is latched on the falling edge of CS. and cleared on
the rising edge of CS. The INT terminal will not clear with
rising edge of CS if a switch contact change has occurred
while CS was low.
In a multiple 33975 device system with WAKE high and
VDD on (Sleep mode), the falling edge of INT will place all
33975s in Normal mode.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33975
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PC33975.PDF ] | |
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