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PDF 33395 Data sheet ( Hoja de datos )
| Número de pieza | 33395 | |
| Descripción | Three-Phase Gate Driver IC | |
| Fabricantes | Freescale Semiconductor | |
| Logotipo |  |
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Technical Data
Three-Phase Gate Driver IC
The 33395 simplifies the design of high-power BLDC motor control
design by combining the gate drive, charge pump, current sense, and
protection circuitry necessary to drive a three-phase bridge
configuration of six N-channel power MOSFETs. Mode logic is
incorporated to route a pulse width modulation (PWM) or a
complementary PWM output signal to either low-side or high-side
MOSFETs of the bridge.
Detection and drive circuitry are also incorporated to control a
reverse battery protection high-side MOSFET switch. PWM
frequencies up to 28 kHz are possible. Built-in protection circuitry
prevents damage to the MOSFET bridge as well as the drive IC and
includes overvoltage shutdown, overtemperature shutdown,
overcurrent shutdown, and undervoltage shutdown.
The device is parametrically specified over ambient temperature
range of -40°C ≤ TA ≤ 125°C and 5.5 V ≤ VIGN ≤ 24 V supply.
Features
• Drives Six N-Channel Low RDS(ON) Power MOSFETs
• Built-In Charge Pump Circuitry
• Built-In Current Sense Comparator and Output Drive Current
Limiting
• Built-In PWM Mode Control Logic
• Built-In Circuit Protection
• Designed for Fractional to Integral HP BLDC Motors
• 32-Pin SOIC Wide Body Surface Mount Package
• 33395 Incorporates a <5.0 µs Shoot-Through Suppression Timer
• 33395T Incorporates a <1.0 µs Shoot-Through Suppression Timer
• Pb-Free Packaging Designated by Suffix Code EW
Document Number: MC33395
Rev 4.0, 2/2007
33395
33395T
THREE-PHASE
GATE DRIVER IC
DWB SUFFIX
EW SUFFIX (Pb-FREE)
98ARH99137A
32-PIN SOICW
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
MC33395DWB/R2
32 SOICW
MC33395EW/R2
MCZ33395EW/R2 -40°C to 125°C
MC33395TDWB/R2
32 SOICW
(Pb-Free)
32 SOICW
MC33395TEW/R2
32 SOICW
(Pb-Free)
VPWR
VDD
3
2
MCU
3
33395
VGDH
VIGN
VDD
CP1H
CP1L
CP2H
CP2L
CRES
VIGNP
GDH1
GDH2
GDH3
SRC1
SRC2
SRC3
HSE1–3
MODE0–1 GDL1
PWM
GDL2
LSE1–3
GDL3
-ISENS
AGND
PGND +ISENS
VDD
NH
SS
NH
Figure 1. 33395 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
1 page  
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
VIGN Supply Voltage
VIGNP Load Dump Survival
VIGN
VIGNPLD
-15.5 to 40
-0.3 to 65
VDC
VDC
VDD Logic Supply Voltage (Fail Safe)
VDD
-0.3 to 7.0
VDC
Logic Input Voltage (LSEn, HSEn, PWM, and MODEn)
VIN
0.3 to 7.0
VDC
Start Up Current VIGNP
ESD Voltage (1)
Human Body Model
Machine Model
IVIGNSTARTUP
VESD1
VESD2
100
±500
±200
mA
V
Storage Temperature
TSTG
-65 to 160
°C
Operating Ambient Temperature
TA
-40 to 125
°C
Operating Case Temperature
TC
-40 to 125
°C
Maximum Junction Temperature
TJ 150 °C
Power Dissipation (TA = 25°C)
Peak Package Reflow Temperature During Reflow (2), (3)
PD
TPPRT
1.5
Note 3
W
°C
Thermal Resistance, Junction-to-Ambient
RΘJA
65 °C/W
Notes
1. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in
accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
2. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
3. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33395
5
5 Page 
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
Figure 5). These gate drive outputs supply the peak currents
required to turn ON and hold ON the low-side MOSFETs, as
well as turn OFF the MOSFETs.
VDD FUSE
The VDD supply of the 33395 IC has an internal fuse, which
will blow and set all outputs of the device to OFF, if the VDD
voltage exceeds that stated in the maximum rating section of
the data sheet. When this fuse blows, the device is
permanently disabled.
ISENS INPUTS
The +Isens and -Isens pins are inputs to the internal
current sense comparator. In a typical application, these
would receive a a low-pass filtered voltage derived from a
current sense resistor placed in series with the ground return
of the three-phase output bridge. When triggered by the
comparator, the CL (current limit) bit of the internal error
register is set, and the output gate drive pairs (i.e., GDH1 and
GDL1, GDH2 and GDL2, GDH3 and GDL3), are controlled
such that current will cease flowing through the load (refer to
Table 5, Truth Table, page 12).
OVERTEMPERATURE AND OVERVOLTAGE
SHUTDOWN CIRCUITS
Internal monitoring is provided for both over temperature
conditions and over voltage conditions. When any of these
conditions presents itself to the IC, the corresponding
internally set bits of the error register are set, and the output
gate drive pairs (i.e., GDH1 and GDL1, GDH2 and GDL2,
GDH3 and GDL3), are controlled such that current will cease
flowing through the load (refer to Table 5).
LSE AND HSE INPUT CIRCUITS
The low-side enable input pins (LSE1, LSE2, LSE3) and
high-side enable input pins (HSE1, HSE2, HSE3) form the
input pairs (HSE1 and LSE1, HSE2 and LSE2, HSE3 and
LSE3) which set the logic states of the output gate drive pairs
(i.e., GDH1 and GDL1, GDH2 and GDL2, GDH3 and GDL3)
in accordance with the logic set forth in the Truth Table
(page 12). Typically these inputs are supplied from an MCU
or DSP to provide the phasing of the currents applied to a
brushless dc motor's stator coils via the output MOSFET
pairs.
PWM INPUT
The pulse width modulation input provides a single input
pin to accomplish PWM modulation of the output pairs in
accordance with the states of the Mode 0 and Mode 1 inputs
as set forth in the Truth Table (page 12).
MODE SELECTION INPUTS
The mode selection inputs (Mode 0 and Mode 1)
determine the PWM implementation of the output pairs in
accordance with the logic set forth in the Truth Table
(page 12). PWMing can thus be set to occur either on the
high-side MOSFETs or the low-side MOSFETs, or can be set
Analog Integrated Circuit Device Data
Freescale Semiconductor
to occur on both the high-side and low-side MOSFETs as
"complementary chopping".
TEST PIN
This pin should be grounded or left floating (i.e., do not
connect it to the printed circuit board). It is used by the
automated test equipment to verify proper operation of the
internal overtemperature shut down circuitry. This pin is
susceptible to latch-up and therefore may cause erroneous
operation or device failure if connected to external circuitry.
33395
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet 33395.PDF ] | |
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