UPB1008K Datasheet PDF - CEL
| Part Number | UPB1008K | |
| Description | LOW POWER GPS RF RECEIVER | |
| Manufacturers | CEL | |
| Logo |  |
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NEC's LOW POWER
GPS RF RECEIVER
UPB1008K
FEATURES
• LOW POWER CONSUMPTION: 52 mW
• DUAL-CONVERSION IQ DOWN CONVERTER1:
Reference frequency: REFin = 27 MHz
• PSEUDO-BASEBAND WITH 2-BIT DIGITIZED OUTPUT
• ON-CHIP LNA, ON-CHIP FREQUENCY SYNTHESIZER,
IF AGC AMPLIFIER:
with 45 dB typical range of adjustable gain
• SMALL 36 PIN QFN PACKAGE:
Flat lead style for better RF performance
Note:
1. Based on eRide's proprietary GPS DSP architecture
BLOCK DIAGRAM
PIN 1 –
LNA
1stMIX
AGC
OSC
PD
1/2
ADC
ADC
APPLICATIONS
• E911 ENABLED MOBILE PHONE
• IN-VEHICLE NAVIGATION SYSTEMS
• LOW POWER HANDHELD GPS RECEIVER
• PC/PDA+GPS INTEGRATION
• ASSET TRACKING
RF APPLICATION DIAGRAM
DESCRIPTION
NEC's UPB1008K is a Silicon RFIC especially designed for
handheld low power/low cost GPS receivers. The IC com-
bines an LNA, followed by a double-conversion RF/IF
downconverter block and a PLL frequency synthesizer on one
chip. The second IF Freqency is a pseudo- baseband signal
into a on-chip 2-bit A/D converters.The device can operate on
a supply voltage as low as 2.7 V, and is a housed in a small 36
pin QFN (Quad, Flat, No-lead) package, resulting in a very low
power consumption and reduced board space.
NEC's stringent quality assurance and test procedures en-
sure the highest reliability and performance.
1st Mixer
IF filter
LNA
AGC
RF SAW
TANK
/2 /4
Nyquist Filters
2-bit
ADC
2-bit
ADC
ISign
IMag
QSign
QMag
Loop
Filter
/6
/7
/2
PLL Frequency
Counters
/8
/2 Regulator Circuitry
I/Q
Balance
REFin
27 MHz
Reference
Clock
California Eastern Laboratories
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UPB1008K
PIN FUNCTIONS
Pin No.
Symbol
Function and Application
1
GNDlna
Ground pin of LNA
2
LNAin
Input pin of low noise amplifier. It is a
single-ended open collector design.
Capacitive coupling is required; external
matching will improve gain or NF.
3
VCCrf
Supply voltage pin of LNA, RF mixer and VCO
voltage regulator.
4
GNDlo
Ground pin of 1st LO Oscillator circuit and RF
Mixer.
5 1stLO-OSC1 Pin 5 & 6 are base pins of the differential
6 1stLO-OSC2 amplifier for 1st LO oscillator. These pins
require an LC (varacator) tank circuit to
oscillate at around 1400 MHz.
7
VCClo
Supply voltage pin of oscillator circuit for
1st LO Oscillator and RF mixer
8
PDout
This is a current mode charge pump output.
For connection to a passive RC loop filter for driving
external varactor diode of 1stLO-OSC.
9
VCCdig
Supply voltage pin of digital portion of the chip.
10
REFin
Input pin of reference frequency buffer. This pin
should be equipped with external 27 MHz
oscillator (e.g. TCXO).
11
GNDdig
Ground pin of digital portion of the chip.
Internal Equivalent Circuit
3
2
VCC
Regulator
GND
7
36
1
3
r=300
r = 410
r=300
6
VCC
Regulator
GND
r=4.4k
idc=941u
5
r=4.4k
4
9
Source Control
Sink Control
9
ESD
8
ESD
11
ESD
r=20k
r=20k
10
ESD
r=500
r=500
idc=9.7u
idc=22u
c=5.4p
r=30k
11
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for UPB1008K electronic component. |
| Information | Total 10 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ UPB1008K.PDF Datasheet ] | |
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