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Numéro de référence | VRS51L3074 | ||
Description | FRAM-enhanced high performance 8051-based microcontroller coupled | ||
Fabricant | Ramtron Corporation | ||
Logo | |||
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VRS51L3074
9 SPI Interface
The SPI interface of the VRS51L3074’s provides
numerous enhancements compared to other vendor
offerings. The SPI interface’s key features include:
• Supports four standard SPI modes (clock
phase/polarity)
• Operates in master and slave modes
• Automatic control of up to four chip select lines
• Configurable transaction size (1 to 32 bits)
• Transaction size of >32 bits is possible
• Double Rx and TX data buffers
• Configurable MSB or LSB first transaction
• Generation frame select/load signals
FIGURE 14: SPI INTERFACE OVERVIEW
Before the SPI can be accessed it must first be
enabled by setting the SPIEN bit of the PERIPHEN1
register to 1.
9.1 SPI Control Registers
The SPICTRL register controls the operating modes of
the SPI interface in master mode.
TABLE 97:SPI CONTROL REGISTER - SPICTRL SFR C1H
7 65 4 3 2
R/W
R/W
R/W
R/W
R/W
R/W
0 00 0 0
0
1
R/W
0
0
R/W
1
Bit Mnemonic Description
7 SPICLK[2:0] SPI Communication Speed (Master Mode)
000 = Sys Clk / 2 ( / 8 if SPISLOW = 1)
001 = Sys Clk / 4 ( / 16 if SPISLOW = 1)
010 = Sys Clk / 8 ( / 32 if SPISLOW = 1)
011 = Sys Clk / 16 ( / 64 if SPISLOW = 1)
100 = Sys Clk / 32 ( / 128 if SPISLOW = 1)
101 = Sys Clk / 64 ( / 256 if SPISLOW = 1)
110 = Sys Clk / 128 ( / 512 if SPISLOW = 1)
111 = Sys Clk / 256 ( / 1024 if SPISLOW = 1)
4
SPICS[1:0]
SPI Active Chip Select Line (Master Mode)
00 = CS0 is active
01 = CS1 is active
10 = CS2 is active
11 = CS3 is active
2
SPICLKPH
SPI Clock Phase
0 = SD0 output on rising edge and SDI
sampling on falling edge
1= SD0 output on falling edge and SDI sampling
on rising edge
1 SPICLKPOL SPI Clock Polarity
0 = SCK stays at 0 when SPI is inactive
1 = SCK stays at 1 when SPI is inactive
0 SPIMASTER SPI Master Mode Enable
0 = SPI operates in slave mode
1 = SPI operate in master mode (default)
When the SPIMASTER bit is set to 1, the SPI interface
operates in master mode. This is the default operating
mode of the VRS51L3074 SPI interface after reset.
9.2 Setting Up Clock Phase and Polarity
The clock phase and polarity is controlled by the
SPICLKPH and SPICLKPOL bits, respectively. The
following diagrams show the communication timing
associated with the clock phase and polarity.
SPI Mode 0:
FIGURE 15: SPI MODE 0
SPI MODE 0: SPICKPOL =0,SPICKPH =1 (Normal Mode Shown)
CSX
SCK
SDO
MSB
SDI
*Arrows indicate the edge where the data acquisition occurs
LSB
www.ramtron.com
page 51 of 105
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Pages | Pages 30 | ||
Télécharger | [ VRS51L3074 ] |
No | Description détaillée | Fabricant |
VRS51L3074 | FRAM-enhanced high performance 8051-based microcontroller coupled | Ramtron Corporation |
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