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PDF XR16M752 Data sheet ( Hoja de datos )
| Número de pieza | XR16M752 | |
| Descripción | HIGH PERFORMANCE DUART | |
| Fabricantes | Exar Corporation | |
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XR16M752/XR68M752
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
MAY 2007
REV. 1.0.2
GENERAL DESCRIPTION
The XR16M752/XR68M7521 (M752) is a high
performance dual universal asynchronous receiver
and transmitter (UART) with 64 byte TX and RX
FIFOs. The M752 operates from 1.62 to 3.63 volts. It
is pin-to-pin and software compatible to the
TL16C752B and SC16C752B, but with additional
features such as a programmable fractional baud rate
generator, automatic RS-485 half-duplex direction
control, infrared mode and 8X and 4X sampling rate.
The standard features include 16 selectable TX and
RX FIFO trigger levels, automatic hardware (RTS/
CTS) and software (Xon/Xoff) flow control, and a
complete modem interface. Onboard registers
provide the user with operational status and data
error flags. An internal loopback capability allows
system diagnostics. Each channel is independently
programmable for data rates up to 16 Mbps at 3.3
Volt with a 4X sampling rate. The XR68M752 has an
additional 16/68# pin to select between the Intel and
Motorola bus interface. The M752 is available in the
48-pin TQFP and 32-pin QFN packages.
NOTE: 1 Covered by U.S. Patent #5,649,122
APPLICATIONS
• Portable Appliances
• Telecommunication Network Routers
• Ethernet Network Routers
• Cellular Data Devices
• Factory Automation and Process Controls
FEATURES
• 1.62 to 3.6 Volt Operation
• Pin-to-pin and software compatible to TI’s
TL16C752B and Philips’ SC16C752B in the 48-
TQFP package
• Two independent UART channels
■ Data rate of up to 16 Mbps at 3.3 V
■ Data rate of up to 12.5 Mbps at 2.5 V
■ Data rate of up to 8 Mbps at 1.8 V
■ Fractional Baud Rate Generator
■ Data sampling rates of 16X, 8X and 4X
■ Transmit and Receive FIFOs of 64 bytes
■ Programmable TX and RX FIFO Trigger Levels
■ Automatic Hardware (RTS/CTS) Flow Control
■ Automatic Software (Xon/Xoff) Flow Control
■ Halt and Resume Transmission Control
■ Automatic RS-485 Half-duplex Direction
Control Output via RTS#
■ Wireless Infrared (IrDA 1.0) Encoder/Decoder
■ Automatic sleep mode
■ Full modem interface
• Crystal oscillator (up to 24MHz) or external clock
(up to 64MHz) input
• 48-TQFP and 32-QFN packages
FIGURE 1. XR16M752 BLOCK DIAGRAM
A2:A0
D7:D0
IOR# (NC)
IOW# (R/W#)
CSA# (CS#)
CSB# (A3)
INTA (IRQ#)
INTB (NC)
TXRDYA#
TXRDYB#
RXRDYA#
RXRDYB#
Reset/Reset#
16/68#
8-bit Data
Bus
Interface
UART Channel A
UART 64 Byte TX FIFO
Regs
TX & RX
IR
ENDEC
BRG
64 Byte RX FIFO
UART Channel B
(same as Channel A)
Crystal Osc/Buffer
1.62 to 3.63 Volt VCC
GND
TXA, RXA, DTRA#,
DSRA#, RTSA#,
DTSA#, CDA#, RIA#,
OP2A#
TXB, RXB, DTRB#,
DSRB#, RTSB#,
CTSB#, CDB#, RIB#,
OP2B#
XTAL1
XTAL2
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
www.DataSheet4U.com
REV. 1.0.2
Pin Description
NAME
CTSA#
32-QFN
PIN #
25
DTRA#
DSRA#
CDA#
RIA#
OP2A#
-
-
-
-
-
TXB 6
RXB
3
RTSB#
15
CTSB#
16
DTRB#
DSRB#
CDB#
RIB#
-
-
-
-
XR16M752/XR68M752
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
48-TQFP
PIN #
38
34
39
40
41
32
8
4
22
23
35
20
16
21
TYPE
DESCRIPTION
I UART channel A Clear-to-Send (active low) or general purpose input.
It can be used for auto CTS flow control, see EFR[7] and IER[7]. This
input should be connected to VCC or GND when not used.
O UART channel A Data-Terminal-Ready (active low) or general purpose
output. If it is not used, leave it unconnected.
I UART channel A Data-Set-Ready (active low) or general purpose input.
This input should be connected to VCC or GND when not used.
I UART channel A Carrier-Detect (active low) or general purpose input.
This input should be connected to VCC or GND when not used.
I UART channel A Ring-Indicator (active low) or general purpose input.
This input should be connected to VCC or GND when not used.
O Output Port 2 Channel A - The output state is defined by the user and
through the software setting of MCR[3]. INTA is set to the active mode
and OP2A# output LOW when MCR[3] is set to a logic 1. INTA is set to
the three state mode and OP2A# output HIGH when MCR[3] is set to a
logic 0. See MCR[3]. If INTA is used, this output should not be used as
a general output else it will disturb the INTA output functionality.
O UART channel B Transmit Data or infrared encoder data. Standard
transmit and receive interface is enabled when MCR[6] = 0. In this
mode, the TX signal will be HIGH during reset or idle (no data). Infrared
IrDA transmit and receive interface is enabled when MCR[6] = 1. In the
Infrared mode, the inactive state (no data) for the Infrared encoder/
decoder interface is LOW. If it is not used, leave it unconnected.
I UART channel B Receive Data or infrared receive data. Normal receive
data input must idle HIGH. The infrared receiver pulses typically idles at
logic 0 but can be inverted by software control prior going in to the
decoder, see MCR[6]. If this pin is not used, tie it to VCC or pull it high
via a 100k ohm resistor.
O UART channel B Request-to-Send (active low) or general purpose out-
put. This port must be asserted prior to using auto RTS flow control,
see EFR[6] and IER[6]. For auto RS485 half-duplex direction control,
see DLD[6].
I UART channel B Clear-to-Send (active low) or general purpose input.
It can be used for auto CTS flow control, see EFR[7] and IER[7]. This
input should be connected to VCC or GND when not used.
O UART channel B Data-Terminal-Ready (active low) or general purpose
output. If it is not used, leave it unconnected.
I UART channel B Data-Set-Ready (active low) or general purpose input.
This input should be connected to VCC or GND when not used.
I UART channel B Carrier-Detect (active low) or general purpose input.
This input should be connected to VCC or GND when not used.
I UART channel B Ring-Indicator (active low) or general purpose input.
This input should be connected to VCC or GND when not used.
5
5 Page 
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XR16M752/XR68M752
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
2.7 Crystal Oscillator or External Clock Input
The M752 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. Please note that the input XTAL1 is not
5V tolerant and so the maximum at the pin should be VCC. For programming details, see ““Section 2.8,
Programmable Baud Rate Generator with Fractional Divisor” on page 11.”
FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS
XTAL1
XTAL2
R1
0-120 Ω
R2 (Optional)
500 ΚΩ− 1 ΜΩ
Y1
1.8432 MHz
to
24 MHz
C1
22-47 pF
C2
22-47 pF
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100 ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 4). The programmable Baud
Rate Generator is capable of operating with a crystal oscillator frequency of up to 24 MHz. However, with an
external clock input on XTAL1 pin, it can extend its operation up to 64 MHz (16 Mbps serial data rate) at 3.3V
with an 4X sampling rate. For further reading on the oscillator circuit please see the Application Note DAN108
on the EXAR web site at http://www.exar.com.
2.8 Programmable Baud Rate Generator with Fractional Divisor
Each UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter and receiver. The
prescaler is controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide
the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG further
divides this clock by a programmable divisor between 1 and (216 - 0.0625) in increments of 0.0625 (1/16) to
obtain a 16X, 8X or 4X sampling clock of the serial data rate. The sampling clock is used by the transmitter for
data bit shifting and receiver for data sampling. The BRG divisor (DLL, DLM and DLD registers) defaults to the
value of ’1’ (DLL = 0x01, DLM = 0x00 and DLD = 0x00) upon reset. Therefore, the BRG must be programmed
during initialization to the operating data rate. The DLL and DLM registers provide the integer part of the divisor
and the DLD register provides the fractional part of the dvisior. The four lower bits of the DLD are used to select
a value from 0 (for setting 0000) to 0.9375 or 15/16 (for setting 1111). Programming the Baud Rate Generator
Registers DLL, DLM and DLD provides the capability for selecting the operating data rate. Table 6 shows the
standard data rates available with a 24MHz crystal or external clock at 16X clock rate. If the pre-scaler is used
(MCR bit-7 = 1), the output data rate will be 4 times less than that shown in Table 6. At 8X sampling rate, these
data rates would double and at 4X sampling rate, these data rates would quadruple. Also, when using 8X
sampling mode, the bit time will have a jitter of ± 1/16 whenever the DLD is non-zero and is an odd number.
11
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| PDF Descargar | [ Datasheet XR16M752.PDF ] | |
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