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PDF LM2512 Data sheet ( Hoja de datos )
| Número de pieza | LM2512 | |
| Descripción | Mobile Pixel Link Level 0 / 24-Bit RGB Display Interface Serializer | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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www.DataSheet4U.com
June 2007
LM2512
Mobile Pixel Link Level 0, 24-Bit RGB Display Interface
Serializer with Dithering and Look Up Table Option
General Description
The LM2512 is a MPL Serializer (SER) that performs a 24-bit
to 18-bit Dither operation and serialization of the video signals
to Mobile Pixel link (MPL) levels on only 3 or 4 active signals.
An optional Look Up Table (Three X 256 X 8 bit RAM) is also
provided for independent color correction. 18-bit Bufferless or
partial buffer displays from QVGA (320 x 240) up to VGA (640
x 480) pixels can utilize a 24-bit video source.
The interconnect is reduced from 28 signals to only 3 or 4
active signals with the LM2512 and companion deserializer
easing flex interconnect design, size constraints and cost.
The LM2512 SER resides by the application, graphics or
baseband processor and translates the wide parallel video
bus from LVCMOS levels to serial Mobile Pixel Link levels for
transmission over a flex cable (or coax) and PCB traces to the
DES located near or in the display module.
When in Power_Down, the SER is put to sleep and draws less
than 10μA. The link can also be powered down by stopping
the PCLK (DES dependant) or by the PD* input pins.
The LM2512 implements the physical layer of the MPL Level
0 Standard (MPL-0) and a 450 μA IOMS current (Class 0).
Features
■ 24-bit RGB Display Interface support up to 640 x 480 VGA
formats
■ 24 to 18-bit Dithering
■ Optional Look Up Table for independent color correction
■ MPL-Level 0 Physical Layer
■ SPI Interface for Look Up Table control and loading
■ Low Power Consumption & Powerdown state
■ Level translation between host and display
■ Optional Auto Power Down on STOP PCLK
■ Frame Sequence bits automatically resync upon data or
clock error
■ 1.6V to 2.0V core / analog supply voltage
■ 1.6V to 3.0V I/O supply voltage range
System Benefits
■ Dithered Data Reduction
■ Independent RGB Color Correction
■ 24-bit Color Input
■ Small Interface
■ Low Power
■ Low EMI
■ Intrinsic Level Translation
Typical 3 MD Lane Application Diagram - Bridge Chip
Ordering Information
NSID
LM2512SM
LM2512SN
Package Type
49L UFBGA, 4.0 X 4.0 X 1.0 mm, 0.5 mm pitch
40L LLP, 6.0 X 6.0 X 0.4 mm, 0.5 mm pitch
© 2007 National Semiconductor Corporation 201728
20172801
Package ID
SLH49A
SNA40A
www.national.com
1 page  
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Recommended Input Timing Requirements (PCLK and SPI)
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2)
Symbol
Parameter
Conditions
Min Typ
PIXEL CLOCK (PCLK)
fPCLK
Pixel Clock Frequency
3 MD Lane, (4X)
2 MD Lane, (6X)
7.5
5
PCLKDC
tT
tSTOPpclk
Pixel Clock Duty Cycle
Transition Time
Clock Stop Gap
(Notes 7, 11)
(Notes 9, 11)
30 50
2 >2
42
SPI INTERFACE
fSCLw
fSCLr
ts0
ts1
th1
tw1h
SCL Frequency
CSX Set Time
SI Set Time
SI Hold Time
SCL Pulse Width High
tw1l SCL Pulse Width Low
tr SCL Rise Time
tf SCL Fall Time
t0H SI Hold Time
th0 CSX Hold Time
tw2 CSX OFF Time
WRITE
READ
Figure 15
Figures 15, 16
WRITE
READ
WRITE
READ
Figure 15
60
30
30
35
60
35
60
5
5
30
65
100
Max
22.5
15
70
10
6.67
Units
MHz
MHz
%
ns
PCLK
cycles
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for VDDIO = 1.8V and VDD = VDDA = 1.8V and TA = 25°C.
Note 3: Current into a device pin is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to Ground unless otherwise
specified.
Note 4: For IDD tests - input signal conditions are: (swing, edge, freq, DE = H, VS = L, HS = L, RGB Checkerboard Pattern: AAAAAA-555555)
Note 5: Total Supply Current Conditions: checkerboard data pattern, 20MHz PCLK (3MDs), TYP VDDIO = VDDA = VDD = 1.8V, MAX VDDIO = 3.0V, MAX VDDA
= VDD = 2.0V.
Note 6: Enable Time is a complete MPL start up comprised of t0 + t1 + t2 + t3 + t4.
Note 7: Maximum transition time is a function of clock rate and should be less than 30% of the clock period to preserve signal quality.
Note 8: Guaranteed functionally by the IDDZ parameter. See also Figure 10.
Note 9: This is the minimum time that the PCLK needs to be held off for in order for the device to be reset. Once PCLK is reapplied, a PLL Lock is required and
start up sequence before video data is serialized.
Note 10: 1 UI is the serial data MD pulse width = 1 / 8xPCLK (3 MD lanes)
Note 11: This is a functional parameter and is guaranteed by design or characterization.
Note 12: Upon power-up, the LUT SRAMs may not be in their lowest power state. To ensure that the SRAMs have entered their lowest power state, a single SPI
access to each of the three SRAMs is recommended. The IDDz current specification assumes that each of the three SRAMs has been accessed at least once.
For additional information, please refer to the "Power Up Sequence" section in the datasheet.
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LOOK UP TABLE OPTION AND SPI INTERFACE
Three 256 X 8-bit SRAMs provide a Look Up Table for inde-
pendent color correction. The LUT is disabled by default and
also after a device PD* cycle. The PD* cycle can be entered
via the PD* input pin directly, or by stopping the PCLK. Before
using the LUT, the SRAM must be loaded with its contents. If
power is cycled to the device, the LUT must be loaded again.
To enable the LUT:
1. Select/Unlock the LM2512 SPI Interface - Write FF’h to
REG22 (16’h)
2. Write the LUT contents to the SRAM using Writes or
Page Writes
3. Access each of the three SRAM at least once to ensure
that they are in their lowest power state.
4. Enable the LUT - Write a 01’h to REG0 (00’h)
5. De-Select/Lock the LM2512 SPI interface -Write 00’h to
REG22 (16’h)
When waking up the LM2512 from the power down mode
(PD*=L), the LUT needs to be enabled if it is desired. Contents
to the SRAM are still held and valid.
1. Select/Unlock the LM2512 SPI Interface - Write FF’h to
REG22 (16’h)
2. Enable the LUT - Write a 01’h to REG0 (00’h)
3. Optional -select Lane Scale if not using default
4. De-Select/Lock the LM2512 SPI interface -Write a 00’h
to REG22 (16’h)
If power is cycled to the device, the LUT SRAMs must be
loaded again.
SPI Interface
The Serial Peripheral Interface (SPI) allows control over var-
ious aspects of the LM2512, the Look Up Table operation,
and access to the three 256 x 8-RAM blocks. There are 9
defined registers in the device. Three SPI transactions are
supported, which are: 16-bit WRITE, PAGE WRITE, and a 16-
bit READ. The SPI interface is disabled when the device is in
the sleep mode (via PCLK Stop or by PD* = L). The SPI in-
terface may be used when PD* = H.
16-bit WRITE
The 16-bit WRITE is shown in 16-bit WRITE – SPI. The SDA
payload consists of a "0" (Write Command), seven address
bits and eight data bits. The CSX signal is driven Low, and
16-bits of SDA (data) are sent to the device. Data is latched
on the rising edge of the SCL. After each 16-bit WRITE, CSX
must return HIGH.
16-bit WRITE – SPI
Bit B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
SDA 0 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
16-bit READ
The 16-bit READ is shown in 16-bit READ – SPI. The SDA
payload consists of a "1" (Read Command), seven address
bits and eight data bits which are driven from the device. The
CSX signal is driven Low, and the host drives the first 8 bits
of the SDA ("1" and seven address bits), the device then
drives the respective 8 bits of the data on the SDA signal.
16-bit READ – SPI
Bit B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
SDA 1 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
PAGE WRITE
The PAGE WRITE is shown in Figure 17. The SDA payload
consists of a "0" (Write Command), seven address bits of the
start address and then the consecutive data bytes. 256 bytes
maximum can be sent. The CSX signal is driven Low, and the
host drives the SDA signal with a "0" (Write Command), the
seven start address bits and the variable length data bytes.
The Page Write is denoted by the CSX signal staying low
while the data bytes are streamed. Data is latched on the ris-
ing edge of the SCL.
PAGE WRITE
Bit B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
SDA 0 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
(start address)
(Data Byte 0)
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
(Data Byte 1)
(Data Byte n, 256 max.)
There are three SPI Interface signals: CSX - SPI Chip Select,
SCL - SPI Clock, and SDA - SPI Data. CSX and SCL are
inputs on the LM2512. SDA is a bi-directional Data line and
is an input for a WRITE and an output for the READ_DATA
portion of a READ operation. READs are optional and are not
required. Due to the Select/Unlock – De-Select/Lock feature
of the device the SPI interface may be shared with the display
driver. Several connection configurations are possible. A cou-
ple examples are shown in Figure 13 and Figure 14.
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| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet LM2512.PDF ] | |
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