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PDF 56F8357 Data sheet ( Hoja de datos )
| Número de pieza | 56F8357 | |
| Descripción | (56F8157 / 56F8357) 16-BIT HYBRID CONTROLLERS | |
| Fabricantes | Freescale Semiconductor | |
| Logotipo |  |
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56F8357/56F8157
Data Sheet
Preliminary Technical Data
56F8300
16-bit Hybrid Controllers
MC56F8357
Rev. 8.0
10/2004
freescale.com
1 page  
56F8357/56F8157 Features
Part 1 Overview
1.1 56F8357/56F8157 Features
1.1.1 Hybrid Controller Core
• Efficient 16-bit 56800E family hybrid controller engine with dual Harvard architecture
• Up to 60 Million Instructions Per Second (MIPS) at 60 MHz core frequency
• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
• Four 36-bit accumulators, including extension bits
• Arithmetic and logic multi-bit shifter
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Three internal address buses
• Four internal data buses
• Instruction set supports both DSP and controller functions
• Controller-style addressing modes and instructions for compact code
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/EOnCE debug programming interface
1.1.2 Differences Between Devices
Table 1-1 outlines the key differences between the 56F8357 and 56F8157 devices.
Table 1-1 Device Differences
Feature
56F8357
Guaranteed Speed
Program RAM
Data Flash
PWM
CAN
Quad Timer
Quadrature Decoder
Temperature Sensor
Dedicated GPIO
60MHz/60 MIPS
4KB
8KB
2x6
1
4
2x4
1
—
56F8157
40MHz/40 MIPS
Not Available
Not Available
1x6
Not Available
2
1x4
Not Available
7
Freescale Semiconductor
Preliminary
56F8357 Technical Data, Rev. 8.0
5
5 Page 
Architecture Block Diagram
5
JTAG / EOnCE
CHIP
TAP
Controller
pdb_m[15:0]
pab[20:0]
cdbw_m[31:0]
56800E
Boot
Flash
Program
Flash
Program
RAM
24
Address
EMI 16
Data
10 Control
TAP
Linking
Module
xab1[23:0]
xab2[23:0]
Data RAM
External
JTAG Port
cdbr_m[31:0]
xdb2_m[15:0]
Data Flash
IPBus
Bridge
To Flash
Control Logic
Note:
Note:
NOT available on the 56F8157 device.
IPBus
Figure 1-1 System Bus Interfaces
Flash
Memory
Module
Flash memories are encapsulated within the Flash Memory (FM) Module. Flash control is
accomplished by the I/O to the FM over the peripheral bus, while reads and writes are completed
between the core and the Flash memories.
The primary data RAM port is 32 bits wide. Other data ports are 16 bits.
Freescale Semiconductor
Preliminary
56F8357 Technical Data, Rev. 8.0
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 56F8357.PDF ] | |
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