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PDF 56F8346 Data sheet ( Hoja de datos )
| Número de pieza | 56F8346 | |
| Descripción | (56F8146 / 56F8346) 16-bit Digital Signal Controllers | |
| Fabricantes | Freescale Semiconductor | |
| Logotipo |  |
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56F8346/56F8146
Data Sheet
Preliminary Technical Data
56F8300
16-bit Digital Signal Controllers
MC56F8346
Rev. 15
01/2007
freescale.com
1 page  
56F8346/56F8146 General Description
Note: Features in italics are NOT available in the 56F8146 device.
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• Access up to 1MB of off-chip program and data memory
• Chip Select Logic for glueless interface to ROM and
SRAM
• 128KB of Program Flash
• 4KB of Program RAM
• 8KB of Data Flash
• 8KB of Data RAM
• 8KB of Boot Flash
• Up to two 6-channel PWM Modules
• Four 4-channel, 12-bit ADCs
• Temperature Sensor
• Up to two Quadrature Decoders
• Optional On-Chip Regulator
• FlexCAN module
• Two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interfaces (SPIs)
• Up to four general-purpose Quad Timers
• Computer Operating Properly (COP) / Watchdog
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 62 GPIO lines
• 144-pin LQFP Package
OCR_DIS
RSTO EMI_MODE
EXTBOOT
RESET
5
VPP
2
VCAP VDD
47
VSS
5
VDDA
2
VSSA
6 PWM Outputs
PWMA
3 Current Sense Inputs
or GPIOC
3 Fault Inputs
JTAG/
EOnCE
Port
Digital Reg Analog Reg
16-Bit
Low Voltage
56800E Core Supervisor
6 PWM Outputs
PWMB
Program Controller
and
Address
Generation Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Bit
Manipulation
3 Current Sense Inputs
Hardware Looping Unit
Three 16-bit Input Registers
Unit
or GPIOD
Four 36-bit Accumulators
4 Fault Inputs
PAB
4 AD0
4
ADCA
AD1
PDB
CDBR
CDBW
5 VREF
Memory
4
4
AD0
ADCB
AD1
Program Memory
64K x 16 Flash
2K x 16 RAM
XDB2
XAB1
XAB2
Temp_Sense
4K x 16 Boot
PAB
Quadrature
Flash
PDB
R/W Control
System Bus
External
Address Bus
Switch
6
2
8
A0-5 or GPIOA8-13
A6-7 or GPIOE2-3
A8-15 or GPIOA0-7
GPIOB0 or A16
4
Decoder 0 or
Quad
Timer A or
Data Memory
4K x 16 Flash
CDBR
CDBW
GPIOC
8K x 16 RAM
Control
External Data
Bus Switch
7
9
D0-6 or GPIOF9-15
D7-15 or GPIOF0-8
Quadrature
Decoder 1 or
4 Quad
Timer B or
IPBus Bridge (IPBB)
Bus Control 2
WR
RD
GPIOD0-1 or CS2-3
SPI1 or
GPIOC
Quad
Timer C or
Decoding
Peripheral
Device Selects
RW IPAB
Control
IPWDB
IPRDB
PS (CS0) or GPIOD8
DS (CS1) or GPIOD9
2
GPIOE
Quad
Peripherals
Timer D or
GPIOE
Clock
resets
PLL
2
FlexCAN
SPI0 or
GPIOE
SCI1 or
GPIOD
SCI0 or
COP/
Interrupt
GPIOE Watchdog Controller
System
P
O
Integration R
Module
Clock O
Generator
S
C
XTAL
EXTAL
4 22
IRQA IRQB
CLKO
CLKMODE
56F8346/56F8146 Block Diagram - 144 LQFP
Freescale Semiconductor
Preliminary
56F8346 Technical Data, Rev. 15
5
5 Page 
Award-Winning Development Environment
A key application-specific feature of the 56F8146 is the inclusion of one Pulse Width Modulator (PWM)
module. This module incorporates three complementary, individually programmable PWM signal output
pairs and can also support six independent PWM functions to enhance motor control functionality.
Complementary operation permits programmable dead time insertion, distortion correction via current
sensing by software, and separate top and bottom output polarity control. The up-counter value is
programmable to support a continuously variable PWM frequency. Edge-aligned and center-aligned
synchronous pulse width control (0% to 100% modulation) is supported. The device is capable of
controlling most motor types: ACIM (AC Induction Motors); both BDC and BLDC (Brush and Brushless
DC motors); SRM and VRM (Switched and Variable Reluctance Motors); and stepper motors. The PWM
incorporates fault protection and cycle-by-cycle current limiting with sufficient output drive capability to
directly drive standard optoisolators. A “smoke-inhibit”, write-once protection feature for key parameters
is also included. A patented PWM waveform distortion correction circuit is also provided. Each PWM is
double-buffered and includes interrupt controls to permit integral reload rates to be programmable from 1
to 16. The PWM module provides reference outputs to synchronize the Analog-to-Digital Converters
through two channels of Quad Timer C.
The 56F8146 incorporates a Quadrature Decoder capable of capturing all four transitions on the two-phase
inputs, permitting generation of a number proportional to actual position. Speed computation capabilities
accommodate both fast- and slow-moving shafts. An integrated watchdog timer in the Quadrature Decoder
can be programmed with a time-out value to alert when no shaft motion is detected. Each input is filtered
to ensure only true transitions are recorded.
This controller also provides a full set of standard programmable peripherals that include two Serial
Communications Interfaces (SCIs); two Serial Peripheral Interfaces (SPIs); and two Quad Timers. Any of
these interfaces can be used as General Purpose Input/Outputs (GPIOs) if that function is not required. An
internal interrupt controller is also a part of the 56F8146.
1.3 Award-Winning Development Environment
Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.
The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
will support concurrent engineering. Together, PE, CodeWarrior and EVMs create a complete, scalable
tools solution for easy, fast, and efficient development.
1.4 Architecture Block Diagram
Note: Features in italics are NOT available in the 56F8146 device and are shaded in the following figures.
The 56F8346/56F8146 architecture is shown in Figure 1-1 and Figure 1-2. Figure 1-1 illustrates how the
56800E system buses communicate with internal memories, the external memory interface and the IPBus
Bridge. Table 1-2 lists the internal buses in the 56800E architecture and provides a brief description of
their function. Figure 1-2 shows the peripherals and control blocks connected to the IPBus Bridge. The
figures do not show the on-board regulator and power and ground signals. They also do not show the
multiplexing between peripherals or the dedicated GPIOs. Please see Part 2, Signal/Connection
Descriptions, to see which signals are multiplexed with those of other peripherals.
Freescale Semiconductor
Preliminary
56F8346 Technical Data, Rev. 15
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 56F8346.PDF ] | |
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