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PDF EM6522 Data sheet ( Hoja de datos )
| Número de pieza | EM6522 | |
| Descripción | MFP version of EM6622 Ultra Low Power Microcontroller | |
| Fabricantes | EM Microelectronic | |
| Logotipo |  |
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EMwww.DataSheet4U.com
MICROELECTRONIC
-
MARIN
SA
EM6522
MFP version of EM6622
Ultra Low Power Microcontroller with 4x32 LCD Driver
Features
• Low Power - 11 µA active mode, LCD On
- 1.8 µA standby mode, LCD Off
- 0.1 µA sleep mode
@ 3 V, 32 KHz, 25 ºC
• Large Voltage range, 2 to 5.5 V
• 2 clocks per instruction cycle
• 72 basic instructions
• EEPROM 4096 x 16 bits
• RAM 128 x 4 bits
• Max. 12 inputs ; port A, port B, port SP
• Max. 8 outputs ; port B, port SP
• Voltage Level Detector, 8 levels software
selectable from 1.2 V up to 4.0 V
• Melody, 7 tones + silence inclusive 4-bit timer
• Universal 10-bit counter, PWM, event counter
• Prescaler down to 1 second ( crystal = 32 KHz )
• 1/1000 sec 12 bit binary coded decimal counter
with hard or software start/stop function
• LCD 32 Segments, 3 or 4 times multiplexed
• 3 wire serial port , 8 bit, master and slave mode
• 5 external interrupts (port A, serial interface)
• 8 internal interrupts (3x prescaler, BCD counter
2x10-bit counter, melody timer, serial interface)
• timer watchdog and oscillation supervisor
Description
The EM6522 is an advanced single chip CMOS 4-
bit microcontroller. It contains EEPROM, RAM,
LCD driver, power on reset, watchdog timer,
oscillation detection circuit, 10-bit up/down and
event counter, 1ms BCD counter, prescaler,
voltage level detector (Vld), serial interface and
several clock functions. The low voltage feature
and low power consumption make it the most
suitable controller for battery, stand alone and
mobile equipment. The EM6522 is manufactured
using EM Microelectronic’s Advanced Low Power
(ALP) CMOS Process.
Figure 1. Architecture
Figure 2. Pin Configuration, TQFP64 10 x 10 x 1 mm
Typical Applications
• Timing device
• Automotive controls with display
• Intelligent display driver
• Measurement equipment
• Domestic appliance
• Interactive system with display
• Timer / sports timing devices
• Bicycle computers
• Safety and security devices
Copyright © 2005, EM Microelectronic-Marin SA
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EM6522
Chip TQFP DIL
64 64 Signal Name
46 51
43
PSP[0]
47 52
44
PSP[1]
48 53
45
PSP[2]
49 54
46
PSP[3]
50 55
51 56
52 57
53 58
54 59
55 60
56 61
57 62
58 63
59 64
60 1
61 2
62 3
63 4
64 5
47 PB[0]
48 PB[1]
49 PB[2]
50 PB[3]
51 PA[0]
52 PA[1]
53 PA[2]
54 PA[3]
55 Buzzer
56 Strobe
57 Vbat = VDD
58 Vreg
59 Qin/Osc1
60 Qout /Osc2
61 VSS
Function
Input/output , open drain
serial port : SIN
parallel out terminal 0
Output , open drain
serial port : Ready/CS
parallel out terminal 1
Output , open drain
serial port : SOUT
parallel out terminal 2
Input/output , open drain
serial port : SCLK
parallel out terminal 3
Input/output, open drain
port B terminal 0
Input/output, open drain
port B terminal 1
Input/output, open drain
port B terminal 2
Input/output, open drain
port B terminal 3
Input port A terminal 0
Input port A terminal 1
Input port A terminal 2
Input port A terminal 3
Output Buzzer terminal
Output Strobe terminal
Positive power supply
Internal voltage regulator
Crystal terminal 1
Crystal terminal 2
Negative power supply
Remarks
Serial interface data in
or
parallel data[0] in/out
Serial interface Ready CS
or
parallel data[1] in/out
Serial interface data out
or
parallel data[2] in/out
Serial interface clock I/O
or
parallel data[3] in/out
Port B data[0] I/O or
Ck[1] output
Port B data[1] I/O or
Ck[11] output
Port B data[2] I/O or
Ck[16] output
Port B data[3] I/O or
PWM output
TestVar 1 ; Event counter
TestVar 2
TestVar 3
Event counter, MSC start/stop
µP reset state or/and port B write
or sleep flag out
MFP Connection
Connect to minimum 100nF,
MFP connection
32 KHz crystal, MFP connection
32 KHz crystal, MFP connection
ref. terminal, MFP connection
Gray shaded areas : Terminals needed for MFP programming connections (VDD, Vreg, Qin, Qout, Test). See
also Programming connections.
EM Microelectronic-Marin SA cannot assume responsibility for use of any circuitry described other than
circuitry entirely embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA
reserves the right to change the circuitry and specifications without notice at any time. You are strongly urged
to ensure that the information given has not been superseded by a more up-to-date version.
Copyright © 2005, EM Microelectronic-Marin SA
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EM6522
4.4 Digital Watchdog Timer Reset
The digital watchdog is a simple, non-programmable, 2-bit timer, that counts on each rising edge of Ck[1]. It will
generate a system reset if it is not periodically cleared. The watchdog timer function can be inhibited by
activating an inhibit digital watchdog bit (NoLogicWD) located in RegVldCntl. At power up, and after any
system reset, the watchdog timer is activated.
If for any reason the CPU stops, then the watchdog timer can detect this situation and activate the system reset
signal. This function can be used to detect program overrun, endless loops, etc. For normal operation, the
watchdog timer must be reset periodically by software at least every 2.5 seconds (system clock = 32 KHz), or a
system reset signal is generated.
The watchdog timer is reset by writing a ‘1’ to the WDReset bit in the timer. This resets the timer to zero and
timer operation restarts immediately. When a ‘0’ is written to WDReset there is no effect. The watchdog timer
operates also in the standby mode and thus, to avoid a system reset, one should not remain in standby mode
for more than 2.5 seconds.
From a system reset state, the watchdog timer will become active after 3.5 seconds. However, if the watchdog
timer is influenced from other sources (i.e. prescaler reset), then it could become active after just 2.5 seconds.
It is therefore recommended to use the Prescaler IRQHz1 interrupt to periodically reset the watchdog every
second.
It is possible to read the current status of the watchdog timer in RegSysCntl2. After watchdog reset, the
counting sequence is (on each rising edge of CK[1]) : ‘00’, ‘01’, ‘10’, ‘11’ {WDVal1 WDVal0}. When going into
the ‘11’ state, the watchdog reset will be active within ½ second. The watchdog reset activates the system
reset which in turn resets the watchdog. If the watchdog is inhibited it’s timer is reset and therefore always
reads ‘0’.
Table 4.4.1 Watchdog Timer Register RegSysCntl2
Bit Name
Reset
R/W
Description
3
WDReset
0
R/W Reset the Watchdog
1 -> Resets the Logic Watchdog
0 -> No action
The Read value is always '0'
2
SleepEn
0
R/W See Operating modes (sleep)
1
WDVal1
0
R Watchdog timer data Ck[1] divided by 4
0
WDVal0
0
R Watchdog timer data Ck[1] divided by 2
4.5 CPU State after Reset
Reset initializes the CPU as shown in Table 4.5.1 below.
1H
Table 4.5.1 Initial CPU Value after Reset.
Name
Bits
Program counter 0
12
Program counter 1
12
Program counter 2
12
Stack pointer
2
Index register
7
Carry flag
1
Zero flag
1
Halt 1
Instruction register
16
Symbol
PC0
PC1
PC2
SP
IX
CY
Z
HALT
IR
Periphery registers 4 Reg.
Initial Value
hex 000 (as a result of Jump 0)
Undefined
Undefined
PSP[0] selected
Undefined
Undefined
Undefined
0
Jump 0
See peripheral memory map
Copyright © 2005, EM Microelectronic-Marin SA
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet EM6522.PDF ] | |
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