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PDF EM461Mxxxx-xx Data sheet ( Hoja de datos )
| Número de pieza | EM461Mxxxx-xx | |
| Descripción | 64Mb SDRAM | |
| Fabricantes | Eorex | |
| Logotipo |  |
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64Mb SDRAM
Ordering Information
EM 48 2M 32 4 4 V T A – 5 L
EOREX
Logo
EDO/FPM
D-RAMBUS
DDRSDRAM
DDRSGRAM
SGRAM
SDRAM
: 40
: 41
: 42
: 43
: 46
: 48
Density
16M : 16 Mega Bits
8M : 8 Mega Bits
4M : 4 Mega Bits
2M : 2 Mega Bits
1M : 1 Mega Bit
Organization
8 : x8
9 : x9
16 : x16
18 : x18
32 : x32
Refresh
1 : 1K, 8 : 8K
2 : 2K, 6 :16K
4 : 4K
Bank
2 : 2Bank 6 : 16Bank
4 : 4Bank 3 : 32Bank
8 : 8Bank
Interface
V: 3.3V
R: 2.5V
URL: http://www.eorex.com
Email: [email protected]
Rev.01
F: PB free package
Power
Blank : Standard
L : Low power
I : Industrial
Min Cycle Time ( Max Freq.)
-5 : 5ns ( 200MHz )
-6 : 5ns ( 167MHz )
-7 : 7ns ( 143MHz )
-75 : 7.5ns ( 133MHz )
-8 : 8ns ( 125MHz )
-10 : 10ns ( 100MHz )
Revision
A : 1st B : 2nd
C : 3rd D :4th
G: for VGA version only
Package
C: CSP B: uBGA
T: TSOP Q: TQFP
P: PQFP ( QFP )
L: LQFP
1/33
1 page  
Block Diagram
64Mb SDRAM
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
BA0
BA1
Auto/Self
Refresh Counter
Memory
Array
Mode Register Set
S/A & I/O gating
Col. Decoder
Col. Add. Buffer
Col. Add. Counter
Burst Counter
DQM
Write DQM
Control
Data In
Data Out
Read DQM
Control
Timing Register
CLK
/CLK
CKE
/CS /RAS /CAS /WE DQM
DQi
Rev.01
5/33
5 Page 
64Mb SDRAM
Programming the Mode Register
The mode register is programmed by the Mode register set command using
address bits BA through A0 as data inputs. The register retains data until it is
reprogrammed or the device loses power.
Options
BA through A7
/CAS Latency Wrap type Burst Length
A6 through A4
A3 A2 through A0
Following mode register programming, no command can be issued before at least 2
CLK elapsed.
/CAS Latency
/CAS Latency is the most critical of the parameters begin set. It tells the device how
many clocks must elapse before the data will be available.
Burst Length
Burst length is the number of the words that will be output or input in a write cycle.
After a read burst is completed, the output bus will become Hi-Z. The burst length is
programmable as 1,2,4,8 or full page.
Wrap Type ( Burst Sequence )
The wrap type specifies the order in which the burst data will be addressed. This
order is programmable as either Sequence or Interleave. The method chosen will
depend on the type of CPU in the system. Some microprocessor cache systems are
optimized for sequential addressing and others for interleaved.
Rev.01
11/33
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet EM461Mxxxx-xx.PDF ] | |
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