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PDF 74LVQ163 Data sheet ( Hoja de datos )

Número de pieza 74LVQ163
Descripción SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
Fabricantes STMicroelectronics 
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No Preview Available ! 74LVQ163 Hoja de datos, Descripción, Manual

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74LVQ163
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
s HIGH SPEED:
fMAX = 180 MHz (TYP.) at VCC = 3.3 V
s COMPATIBLE WITH TTL OUTPUTS
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA=25°C
s LOW NOISE:
VOLP = 0.3V (TYP.) at VCC = 3.3V
s 75TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 12mA (MIN) at VCC = 3.0 V
s PCI BUS LEVELS GUARANTEED AT 24 mA
s BALANCED PROPAGATION DELAYS:
tPLH tPHL
s OPERATING VOLTAGE RANGE:
VCC(OPR) = 2V to 3.6V (1.2V Data Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 163
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVQ163 is a low voltage CMOS
SYNCHRONOUS PRESETTABLE COUNTER
fabricated with sub-micron silicon gate and
double-layer metal wiring C2MOS technology. It is
ideal for low power and low noise 3.3V
applications. It is a 4 bit binary counter with
Synchronous Clear.
The circuit have four fundamental modes of
operation, in order of preference: synchronous
reset, parallel load, count-up and hold. Four
PIN CONNECTION AND IEC LOGIC SYMBOLS
SOP
TSSOP
ORDER CODES
PACKAGE
SOP
TSSOP
TUBE
74LVQ163M
T&R
74LVQ163MTR
74LVQ163TTR
control inputs, Master Reset (CLEAR), Parallel
Enable Input (LOAD), Count Enable Input (PE)
and Count Enable Carry Input (TE), determine the
mode of operation as shown in the Truth Table. A
LOW signal on CLEAR overrides counting and
parallel loading and allows all outputs to go LOW
on the next rising edge of CLOCK. A LOW signal
on LOAD overrides counting and allows
information on Parallel Data Qn inputs to be
loaded into the flip-flops on the next rising edge of
CLOCK. With LOAD and CLEAR, PE and TE
permit counting when both are high. Conversely, a
LOW signal on either PE and TE inhibits counting.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
July 2001
1/13

1 page




74LVQ163 pdf
74LVQ163
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC Supply Voltage (note 1)
VI Input Voltage
VO Output Voltage
Top Operating Temperature
dt/dv Input Rise and Fall Time VCC = 3.0V (note 2)
1) Truth Table guaranteed: 1.2V to 3.6V
2) VIN from 0.8V to 2V
DC SPECIFICATIONS
Value
2 to 3.6
0 to VCC
0 to VCC
-55 to 125
0 to 10
Unit
V
V
V
°C
ns/V
Test Condition
Value
Symbol
Parameter
VCC
(V)
TA = 25°C
Min. Typ. Max.
VIH High Level Input
Voltage
3.0 to
VIL Low Level Input
Voltage
3.6
2.0
0.8
VOH High Level Output
Voltage
3.0
IO=-50 µA
IO=-12 mA
2.9 2.99
2.58
IO=-24 mA
VOL Low Level Output
Voltage
3.0
IO=50 µA
IO=12 mA
0.002 0.1
0 0.36
IO=24 mA
II Input Leakage
Current
3.6 VI = VCC or GND
± 0.1
ICC
Quiescent Supply
Current
3.6 VI = VCC or GND
4
IOLD
IOHD
Dynamic Output
Current (note 1, 2)
3.6 VOLD = 0.8 V max
VOHD = 2 V min
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75
-40 to 85°C -55 to 125°C
Min. Max. Min. Max.
2.0 2.0
0.8 0.8
2.9 2.9
2.48
2.48
2.2 2.2
0.1 0.1
0.44
0.44
0.55
0.55
±1 ±1
40 40
36 25
-25 -25
Unit
V
V
V
V
µA
µA
mA
mA
5/13

5 Page





74LVQ163 arduino
DIM.
A
a1
a2
b
b1
C
c1
D
E
e
e3
F
G
L
M
S
MIN.
0.1
0.35
0.19
9.8
5.8
3.8
4.6
0.5
SO-16 MECHANICAL DATA
mm.
TYP
0.5
1.27
8.89
MAX.
1.75
0.2
1.65
0.46
0.25
MIN.
0.003
0.013
0.007
45° (typ.)
10 0.385
6.2 0.228
4.0 0.149
5.3 0.181
1.27 0.019
0.62
8° (max.)
74LVQ163
inch
TYP.
0.019
0.050
0.350
MAX.
0.068
0.007
0.064
0.018
0.010
0.393
0.244
0.157
0.208
0.050
0.024
PO13H
11/13

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