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PDF LH28F800BJHB-PTTL90 Data sheet ( Hoja de datos )
| Número de pieza | LH28F800BJHB-PTTL90 | |
| Descripción | 8M (x8/x16) Flash Memory | |
| Fabricantes | Sharp Electrionic | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LH28F800BJHB-PTTL90 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Date Mar. 23. 2001
www.DataSheet4U.com
8M (x8/x16) Flash Memory
LH28F800BJHB-PTTL90
1 page  
LHF80J23
3
1 INTRODUCTION
This datasheet contains the product specifications. Section
1 provides a flash memory overview. Sections 2, 3, 4 and
5 describe the memory organization and functionality.
Section 6 covers electrical specifications.
1.1 Features
Key enhancements of the product are:
•Single low voltage operation
•Low power consumption
•Enhanced Suspend Capabilities
•Boot Block Architecture
Please note following:
•VCCWLK has been lowered to 1.0V to support 2.7V-
3.6V block erase, full chip erase, word/byte write and
lock-bit configuration operations. The VCCW voltage
transitions to GND is recommended for designs that
switch VCCW off during read operation.
1.2 Product Overview
The product is a high-performance 8M-bit Boot Block
Flash memory organized as 512K-word of 16 bits or 1M-
byte of 8 bits. The 512K-word/1M-byte of data is arranged
in two 4K-word/8K-byte boot blocks, six 4K-word/8K-
byte parameter blocks and fifteen 32K-word/64K-byte
main blocks which are individually erasable, lockable and
unlockable in-system. The memory map is shown in
Figure 3.
The dedicated VCCW pin gives complete data protection
when VCCW≤VCCWLK.
A Command User Interface (CUI) serves as the interface
between the system processor and internal operation of the
device. A valid command sequence written to the CUI
initiates device automation. An internal Write State
Machine (WSM) automatically executes the algorithms
and timings necessary for block erase, full chip erase,
word/byte write and lock-bit configuration operations.
A block erase operation erases one of the device’s 32K-
word/64K-byte blocks typically within 1.2s (3V VCC, 3V
VCCW), 4K-word/8K-byte blocks typically within 0.6s (3V
VCC, 3V VCCW) independent of other blocks. Each block
can be independently erased minimum 100,000 times.
Block erase suspend mode allows system software to
suspend block erase to read or write data from any other
block.
Writing memory data is performed in word/byte
increments of the device’s 32K-word blocks typically
within 33µs (3V VCC, 3V VCCW), 64K-byte blocks
typically within 31µs (3V VCC, 3V VCCW), 4K-word
blocks typically within 36µs (3V VCC, 3V VCCW), 8K-
byte blocks typically within 32µs (3V VCC, 3V VCCW).
Word/byte write suspend mode enables the system to read
data or execute code from any other flash memory array
location.
Individual block locking uses a combination of bits, thirty-
nine block lock-bits, a permanent lock-bit and WP# pin, to
lock and unlock blocks. Block lock-bits gate block erase,
full chip erase and word/byte write operations, while the
permanent lock-bit gates block lock-bit modification and
locked block alternation. Lock-bit configuration
operations (Set Block Lock-Bit, Set Permanent Lock-Bit
and Clear Block Lock-Bits commands) set and cleared
lock-bits.
The status register indicates when the WSM’s block erase,
full chip erase, word/byte write or lock-bit configuration
operation is finished.
The RY/BY# output gives an additional indicator of WSM
activity by providing both a hardware signal of status
(versus software polling) and status masking (interrupt
masking for background block erase, for example). Status
polling using RY/BY# minimizes both CPU overhead and
system power consumption. When low, RY/BY# indicates
that the WSM is performing a block erase, full chip erase,
word/byte write or lock-bit configuration. RY/BY#-high Z
indicates that the WSM is ready for a new command,
block erase is suspended (and word/byte write is
inactive), word/byte write is suspended, or the device is in
reset mode.
Rev. 1.27
5 Page 
LHF80J23
9
3.5 Read Identifier Codes
The read identifier codes operation outputs the
manufacturer code, device code, block lock configuration
codes for each block and the permanent lock configuration
code (see Figure 4). Using the manufacturer and device
codes, the system CPU can automatically match the device
with its proper algorithms. The block lock and permanent
lock configuration codes identify locked and unlocked
blocks and permanent lock-bit setting.
[A18-A0]
Top Boot
[A18-A-1]
7FFFF
7F003
7F002
7F001
7F000
7EFFF
7E003
7E002
7E001
7E000
7DFFF
7D003
7D002
7D001
7D000
7CFFF
79000
Reserved for Future Implementation
FFFFF
Boot Block 0 Lock Configuration Code
FE006
FE005
FE004
Reserved for Future Implementation
FE003
Boot Block 0 FE000
Reserved for Future Implementation
FDFFF
Boot Block 1 Lock Configuration Code
FC006
FC005
FC004
Reserved for Future Implementation
FC003
Boot Block 1 FC000
Reserved for Future Implementation
FBFFF
Parameter Block 0 Lock Configuration Code
Reserved for Future Implementation
Parameter Block 0
FA006
FA005
FA004
FA003
FA000
(Parameter Blocks 1 through 4)
F9FFF
F2000
78FFF
78003
78002
78001
78000
77FFF
70003
70002
70001
70000
6FFFF
08000
Reserved for Future Implementation
F1FFF
F0006
Parameter Block 5 Lock Configuration Code
F0005
F0004
Reserved for Future Implementation
F0003
Parameter Block 5 F0000
Reserved for Future Implementation
EFFFF
E0006
Main Block 0 Lock Configuration Code
E0005
E0004
Reserved for Future Implementation
E0003
Main Block 0 E0000
(Main Blocks 1 through 13)
DFFFF
10000
07FFF
01000
Reserved for Future Implementation
0FFFF
02000
00FFF
00080
OTP Block
01FFF
00100
0007F
00004
00003
00002
00001
00000
Reserved for Future Implementation
Permanent Lock Configuration Code
Main Block 14 Lock Configuration Code
Device Code
Manufacturer Code Main Block 14
000FF
00008
00007
00006
00005
00004
00003
00002
00001
00000
Figure 4. Device Identifier Code Memory Map
3.6 OTP(One Time Program) Block
The OTP block is a special block that can not be erased.
The block is divided into two parts. One is a factory
program area where a unique number can be written
according to customer requirements in SHARP factory.
This factory program area is "READ ONLY" (Already
locked). The other is a customer program area that can be
used by customers. This customer program area can be
locked. After locking, this customer program area is
protected permanently.
The OTP block is read in Configuration Read Mode by
writing Read Identifier Codes command(90H). To return
to Read Array Mode, write Read Array command(FFH).
The OTP block is programmed by writing OTP Program
command(C0H). First write OTP Program command and
then write data with address to the device (See Figure 5).
If OTP program is failed, SR.4(WORD/BYTE WRITE
AND SET LOCK-BIT STATUS) bit is set to "1". And if
this OTP block is locked, SR.1(DEVICE PROTECT
STATUS) bit is set to "1" too.
The OTP block is also locked by writing OTP Program
command(C0H). First write OTP Program command and
then write data "FFFDH" with address "80H" to the
device. Address "80H" of OTP block is OTP lock
information. Bit 0 of address "80H" means factory
program area lock status("1" is "NOT LOCKED", "0" is
"LOCKED"). Bit 1 of address "80H" means customer
program area lock status. The OTP lock information can
not be cleared, after once it is set.
[A18-A0]
00FFF
Customer Program Area
[A18-A-1]
01FFF
00085
00084
00081
00080
Factory Program Area
OTP Lock
Customer Program Area Lock(Bit 1)
Factory Program Area Lock(Bit 0)
0010A
00109
00102
00100
Figure 5. OTP Block Address Map
Rev. 1.27
11 Page | ||
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