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PDF LH28F160BHE-TTL90 Data sheet ( Hoja de datos )
| Número de pieza | LH28F160BHE-TTL90 | |
| Descripción | 16M (x8/x16) Flash Memory | |
| Fabricantes | Sharp Electrionic | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LH28F160BHE-TTL90 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Date May. 16. 2000
www.DataSheet4U.com
16M (x8/x16) Flash Memory
LH28F160BHE-TTL90
1 page  
LHF16J04
3
1 INTRODUCTION
This datasheet contains LH28F160BJHE-TTL90
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4 and 5 describe the memory
organization and functionality. Section 6 covers electrical
specifications.
1.1 Features
Key enhancements of LH28F160BJHE-TTL90 boot block
Flash memory are:
•Single low voltage operation
•Low power consumption
•Enhanced Suspend Capabilities
•Boot Block Architecture
Please note following:
•VCCWLK has been lowered to 1.0V to support 2.7V-
3.6V block erase, full chip erase, word/byte write and
lock-bit configuration operations. The VCCW voltage
transitions to GND is recommended for designs that
switch VCCW off during read operation.
1.2 Product Overview
The LH28F160BJHE-TTL90 is a high-performance 16M-
bit Boot Block Flash memory organized as 1M-word of 16
bits or 2M-byte of 8 bits. The 1M-word/2M-byte of data is
arranged in two 4K-word/8K-byte boot blocks, six 4K-
word/8K-byte parameter blocks and thirty-one 32K-
word/64K-byte main blocks which are individually
erasable, lockable and unlockable in-system. The memory
map is shown in Figure 3.
The dedicated VCCW pin gives complete data protection
when VCCW≤VCCWLK.
A Command User Interface (CUI) serves as the interface
between the system processor and internal operation of the
device. A valid command sequence written to the CUI
initiates device automation. An internal Write State
Machine (WSM) automatically executes the algorithms
and timings necessary for block erase, full chip erase,
word/byte write and lock-bit configuration operations.
A block erase operation erases one of the device’s 32K-
word/64K-byte blocks typically within 1.2s (3V VCC, 3V
VCCW), 4K-word/8K-byte blocks typically within 0.6s (3V
VCC, 3V VCCW) independent of other blocks. Each block
can be independently erased minimum 100,000 times.
Block erase suspend mode allows system software to
suspend block erase to read or write data from any other
block.
Writing memory data is performed in word/byte
increments of the device’s 32K-word blocks typically
within 33µs (3V VCC, 3V VCCW), 64K-byte blocks
typically within 31µs (3V VCC, 3V VCCW), 4K-word
blocks typically within 36µs (3V VCC, 3V VCCW), 8K-
byte blocks typically within 32µs (3V VCC, 3V VCCW).
Word/byte write suspend mode enables the system to read
data or execute code from any other flash memory array
location.
Individual block locking uses a combination of bits, thirty-
nine block lock-bits, a permanent lock-bit and WP# pin, to
lock and unlock blocks. Block lock-bits gate block erase,
full chip erase and word/byte write operations, while the
permanent lock-bit gates block lock-bit modification and
locked block alternation. Lock-bit configuration
operations (Set Block Lock-Bit, Set Permanent Lock-Bit
and Clear Block Lock-Bits commands) set and cleared
lock-bits.
The status register indicates when the WSM’s block erase,
full chip erase, word/byte write or lock-bit configuration
operation is finished.
The RY/BY# output gives an additional indicator of WSM
activity by providing both a hardware signal of status
(versus software polling) and status masking (interrupt
masking for background block erase, for example). Status
polling using RY/BY# minimizes both CPU overhead and
system power consumption. When low, RY/BY# indicates
that the WSM is performing a block erase, full chip erase,
word/byte write or lock-bit configuration. RY/BY#-high Z
indicates that the WSM is ready for a new command,
block erase is suspended (and word/byte write is
inactive), word/byte write is suspended, or the device is in
reset mode.
Rev. 1.26
5 Page 
LHF16J04
9
3.5 Read Identifier Codes
The read identifier codes operation outputs the
manufacturer code, device code, block lock configuration
codes for each block and the permanent lock configuration
code (see Figure 4). Using the manufacturer and device
codes, the system CPU can automatically match the device
with its proper algorithms. The block lock and permanent
lock configuration codes identify locked and unlocked
blocks and permanent lock-bit setting.
3.6 Write
Writing commands to the CUI enable reading of device
data and identifier codes. They also control inspection and
clearing of the status register. When VCC=2.7V-3.6V and
VCCW=VCCWH1/2, the CUI additionally controls block
erase, full chip erase, word/byte write and lock-bit
configuration.
The Block Erase command requires appropriate command
data and an address within the block to be erased. The Full
Chip Erase command requires appropriate command data
and an address within the device. The Word/Byte Write
command requires the command and address of the
location to be written. Set Permanent and Block Lock-Bit
commands require the command and address within the
device (Permanent Lock) or block within the device
(Block Lock) to be locked. The Clear Block Lock-Bits
command requires the command and address within the
device.
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are active. The
address and data needed to execute a command are latched
on the rising edge of WE# or CE# (whichever goes high
first). Standard microprocessor write timings are used.
Figures 16 and 17 illustrate WE# and CE# controlled write
operations.
4 COMMAND DEFINITIONS
When the VCCW voltage ≤VCCWLK, read operations from
the status register, identifier codes, or blocks are enabled.
Placing VCCWH1/2 on VCCW enables successful block
erase, full chip erase, word/byte write and lock-bit
configuration operations.
Device operations are selected by writing specific
commands into the CUI. Table 3 defines these commands.
[A19-A0]*
Top Boot
FFFFF
FF003
Reserved for Future Implementation
FF002 Boot Block 0 Lock Configuration Code
FF001
FF000
FEFFF
FE003
FE002
Reserved for Future Implementation
Boot Block 0
Reserved for Future Implementation
Boot Block 1 Lock Configuration Code
FE001
FE000
FDFFF
FD003
FD002
Reserved for Future Implementation
Boot Block 1
Reserved for Future Implementation
Parameter Block 0 Lock Configuration Code
FD001
FD000
FCFFF
F9000
Reserved for Future Implementation
Parameter Block 0
(Parameter Blocks 1 through 4)
F8FFF
F8003
Reserved for Future Implementation
F8002 Parameter Block 5 Lock Configuration Code
F8001
F8000
F7FFF
F0003
Reserved for Future Implementation
Parameter Block 5
Reserved for Future Implementation
F0002 Main Block 0 Lock Configuration Code
F0001
F0000
EFFFF
08000
Reserved for Future Implementation
Main Block 0
(Main Blocks 1 through 29)
07FFF
Reserved for Future Implementation
00004
00003
Permanent Lock Configuration Code
00002 Main Block 30 Lock Configuration Code
00001
Device Code
00000
Manufacturer Code Main Block 30
*: Address A-1 don’t care.
Figure 4. Device Identifier Code Memory Map
Rev. 1.26
11 Page | ||
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