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PDF NH82801HR Data sheet ( Hoja de datos )
| Número de pieza | NH82801HR | |
| Descripción | I/O Controller Hub 8 | |
| Fabricantes | Intel | |
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Intel® I/O Controller Hub 8 (ICH8)
Family
Datasheet
– For the Intel® 82801HB ICH8 and 82801HR ICH8R I/O Controller
Hubs
June 2006
Document Number: 313056-001
1 page  
www.DataSheet4U.com
Contents
5.5.1.2 Rotating Priority ...................................................................................110
5.5.2 Address Compatibility Mode ................................................................................110
5.5.3 Summary of DMA Transfer Sizes ........................................................................110
5.5.3.1 Address Shifting When Programmed for 16-Bit I/O Count by Words ..111
5.5.4 Autoinitialize.........................................................................................................111
5.5.5 Software Commands ...........................................................................................111
5.6 LPC DMA..........................................................................................................................112
5.6.1 Asserting DMA Requests.....................................................................................112
5.6.2 Abandoning DMA Requests ................................................................................112
5.6.3 General Flow of DMA Transfers ..........................................................................113
5.6.4 Terminal Count ....................................................................................................113
5.6.5 Verify Mode..........................................................................................................114
5.6.6 DMA Request Deassertion ..................................................................................114
5.6.7 SYNC Field / LDRQ# Rules .................................................................................115
5.7 8254 Timers (D31:F0).......................................................................................................115
5.7.1 Timer Programming .............................................................................................116
5.7.2 Reading from the Interval Timer ..........................................................................117
5.7.2.1 Simple Read ........................................................................................117
5.7.2.2 Counter Latch Command .....................................................................117
5.7.2.3 Read Back Command ..........................................................................118
5.8 8259 Interrupt Controllers (PIC) (D31:F0) ........................................................................119
5.8.1 Interrupt Handling ................................................................................................120
5.8.1.1 Generating Interrupts ...........................................................................120
5.8.1.2 Acknowledging Interrupts.....................................................................120
5.8.1.3 Hardware/Software Interrupt Sequence...............................................121
5.8.2 Initialization Command Words (ICWx) .................................................................121
5.8.2.1 ICW1 ....................................................................................................121
5.8.2.2 ICW2 ....................................................................................................122
5.8.2.3 ICW3 ....................................................................................................122
5.8.2.4 ICW4 ....................................................................................................122
5.8.3 Operation Command Words (OCW) ....................................................................122
5.8.4 Modes of Operation .............................................................................................122
5.8.4.1 Fully Nested Mode ...............................................................................122
5.8.4.2 Special Fully-Nested Mode ..................................................................123
5.8.4.3 Automatic Rotation Mode (Equal Priority Devices) ..............................123
5.8.4.4 Specific Rotation Mode (Specific Priority) ............................................123
5.8.4.5 Poll Mode .............................................................................................123
5.8.4.6 Cascade Mode .....................................................................................124
5.8.4.7 Edge and Level Triggered Mode..........................................................124
5.8.4.8 End of Interrupt (EOI) Operations ........................................................124
5.8.4.9 Normal End of Interrupt........................................................................124
5.8.4.10 Automatic End of Interrupt Mode .........................................................124
5.8.5 Masking Interrupts ...............................................................................................125
5.8.5.1 Masking on an Individual Interrupt Request.........................................125
5.8.5.2 Special Mask Mode..............................................................................125
5.8.6 Steering PCI Interrupts ........................................................................................125
5.9 Advanced Programmable Interrupt Controller (APIC) (D31:F0) .......................................126
5.9.1 Interrupt Handling ................................................................................................126
5.9.2 Interrupt Mapping.................................................................................................126
5.9.3 PCI / PCI Express* Message-Based Interrupts ...................................................127
5.9.4 Front Side Bus Interrupt Delivery.........................................................................127
Intel® ICH8 Family Datasheet
5
5 Page 
Contents
www.DataSheet4U.com
7.1.63
7.1.64
7.1.65
7.1.66
7.1.67
7.1.68
7.1.69
7.1.70
7.1.71
7.1.72
D25IR—Device 25 Interrupt Route Register........................................................257
OIC—Other Interrupt Control Register.................................................................258
RC—RTC Configuration Register ........................................................................258
HPTC—High Precision Timer Configuration Register .........................................259
GCS—General Control and Status Register........................................................259
BUC—Backed Up Control Register .....................................................................261
FD—Function Disable Register ...........................................................................261
FDSW—Function Disable SUS Well....................................................................263
CIR8—Chipset Initialization Register 8................................................................264
CIR9—Chipset Initialization Register 9................................................................264
8 Gigabit LAN Configuration Registers ......................................................................................265
8.1 Gigabit LAN Configuration Registers (Gigabit LAN — D25:F0)........................................265
8.1.1 VID—Vendor Identification Register (Gigabit LAN—D25:F0) ..............................266
8.1.2 DID—Device Identification Register (Gigabit LAN—D25:F0) ..............................266
8.1.3 PCICMD—PCI Command Register (Gigabit LAN—D25:F0) ...............................267
8.1.4 PCISTS—PCI Status Register (Gigabit LAN—D25:F0).......................................268
8.1.5 RID—Revision Identification Register (Gigabit LAN—D25:F0)............................269
8.1.6 CC—Class Code Register (Gigabit LAN—D25:F0) .............................................269
8.1.7 CLS—Cache Line Size Register (Gigabit LAN—D25:F0)....................................269
8.1.8 PLT—Primary Latency Timer Register (Gigabit LAN—D25:F0) ..........................269
8.1.9 HT—Header Type Register (Gigabit LAN—D25:F0) ...........................................270
8.1.10 MBARA—Memory Base Address Register A (Gigabit LAN—D25:F0) ................270
8.1.11 MBARB—Memory Base Address Register B (Gigabit LAN—D25:F0) ................270
8.1.12 MBARC—Memory Base Address Register C (Gigabit LAN—D25:F0)................271
8.1.13 SID—Subsystem ID Register (Gigabit LAN—D25:F0) ........................................271
8.1.14 SVID—Subsystem Vendor ID Register (Gigabit LAN—D25:F0) .........................271
8.1.15 ERBA—Expansion ROM Base Address Register (Gigabit LAN—D25:F0) .........272
8.1.16 CAPP—Capabilities List Pointer Register (Gigabit LAN—D25:F0) .....................272
8.1.17 INTR—Interrupt Information Register (Gigabit LAN—D25:F0) ............................272
8.1.18 MLMG—Maximum Latency/Minimum Grant Register (Gigabit LAN—D25:F0) ...272
8.1.19 CLIST 1—Capabilities List Register 1(Gigabit LAN—D25:F0) ............................273
8.1.20 PMC—PCI Power Management Capabilities Register (Gigabit LAN—D25:F0) ..273
8.1.21 PMCS—PCI Power Management Control and Status
Register (Gigabit LAN—D25:F0) .........................................................................274
8.1.22 DR—Data Register (Gigabit LAN—D25:F0) ........................................................274
8.1.23 CLIST 2—Capabilities List Register 2 (Gigabit LAN—D25:F0) ...........................275
8.1.24 MCTL—Message Control Register (Gigabit LAN—D25:F0)................................275
8.1.25 MADDL—Message Address Low Register (Gigabit LAN—D25:F0)....................275
8.1.26 MADDH—Message Address High Register (Gigabit LAN—D25:F0) ..................276
8.1.27 MDAT—Message Data Register (Gigabit LAN—D25:F0) ...................................276
8.2 GBAR0—Gigabit LAN Base Address Register 0 Registers..............................................276
8.2.1 LDCR1—LAN Device Control Register 1
(Gigabit LAN Memory Mapped Base Address Register) .....................................276
8.2.2 LDCR2—LAN Device Control Register 2
(Gigabit LAN Memory Mapped Base Address Register) .....................................277
8.2.3 LDR1—LAN Device Initialization Register 1
(Gigabit LAN Memory Mapped Base Address Register) .....................................277
8.2.4 EXTCNF_CTRL—Extended Configuration Control Register
(Gigabit LAN Memory Mapped Base Address Register) .....................................277
Intel® ICH8 Family Datasheet
11
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet NH82801HR.PDF ] | |
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