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PDF 56F826 Data sheet ( Hoja de datos )
| Número de pieza | 56F826 | |
| Descripción | 16-bit Digital Signal Controllers | |
| Fabricantes | Freescale Semiconductor | |
| Logotipo |  |
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56F826
Data Sheet
Preliminary Technical Data
56F800
16-bit Digital Signal Controllers
www.DataSheet4U.com
DSP56F826
Rev. 14
01/2007
freescale.com
1 page  
56F826 Description
• Sixteen (16) dedicated General Purpose I/O (GPIO) pins
• Thirty (30) shared General Purpose I/O (GPIO) pins
• Computer-Operating Properly (COP) Watchdog timer
• Two external interrupt pins
• External reset pin for hardware reset
• JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging
• Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock
• Fabricated in high-density EMOS with 5V-tolerant, TTL-compatible digital inputs
• One Time of Day module
1.1.4 Energy Information
• Dual power supply, 3.3V and 2.5V
• Wait and Multiple Stop modes available
1.2 56F826 Description
The 56F826 is a member of the 56800 core-based family of processors. It combines, on a single chip, the
processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to
create an extremely cost-effective solution for general purpose applications. Because of its low cost,
configuration flexibility, and compact program code, the 56F826 is well-suited for many applications.
The 56F826 includes many peripherals that are especially useful for applications such as: noise
suppression, ID tag readers, sonic/subsonic detectors, security access devices, remote metering, sonic
alarms, POS terminals, feature phones.
The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
DSP and MCU applications. The instruction set is also highly efficient for C/C++ Compilers to enable
rapid development of optimized control applications.
The 56F826 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F826 also provides two external
dedicated interrupt lines, and up to 46 General Purpose Input/Output (GPIO) lines, depending on
peripheral configuration.
The 56F826 controller includes 31.5K words (16-bit) of Program Flash and 2K words of Data Flash (each
programmable through the JTAG port) with 512 words of Program RAM, and 4K words of Data RAM. It
also supports program execution from external memory.
The 56F826 incorporates a total of 2K words of Boot Flash for easy customer-inclusion of
field-programmable software routines that can be used to program the main Program and Data Flash
memory areas. Both Program and Data Flash memories can be independently bulk-erased or erased in page
sizes of 256 words. The Boot Flash memory can also be either bulk- or page-erased.
Freescale Semiconductor
56F826 Technical Data, Rev. 14
5
5 Page 
Signals and Package Information
Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)
Signal
Name
XTAL
Pin No.
62
Type
Output
Description
Crystal Oscillator Output—This output connects the internal crystal oscillator
output to an external crystal or ceramic resonator. If an external clock source
over 4MHz is used, XTAL must be used as the input and EXTAL connected to
VSS. For more information, please refer to Section 3.6.3.
(CLOCKIN)
Input
External Clock Input—This input should be asserted when using an external
clock or ceramic resonator.
CLKO
65
Output
Clock Output—This pin outputs a buffered clock signal. By programming the
CLKO Select Register (CLKOSR), the user can select between outputting a
version of the signal applied to XTAL and a version of the device master clock at
the output of the PLL. The clock frequency on this pin can be disabled by
programming the CLKO Select Register (CLKOSR).
A0
(GPIOE0)
24
Output
Address Bus—A0–A7 specify the address for external program or data memory
accesses.
A1
(GPIOE1)
A2
(GPIOE2)
23 Input/Output Port E GPIO—These eight General Purpose I/O (GPIO) pins can be individually
programmed as input or output pins.
22
After reset, the default state is Address Bus.
A3
(GPIOE3)
21
A4
(GPIOE4)
18
A5
(GPIOE5)
17
A6
(GPIOE6)
16
A7 15
(GPIOE7)
Freescale Semiconductor
56F826 Technical Data, Rev. 14
11
11 Page | ||
| Páginas | Total 56 Páginas | |
| PDF Descargar | [ Datasheet 56F826.PDF ] | |
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