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PDF 56857 Data sheet ( Hoja de datos )
| Número de pieza | 56857 | |
| Descripción | 16-bit Digital Signal Controllers | |
| Fabricantes | Freescale Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 56857 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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56857
Data Sheet
Technical Data
56800E
16-bit Digital Signal Controllers
www.DataSheet4U.com
DSP56857
Rev. 6
01/2007
freescale.com
1 page  
56857 Description
• 8-bit Parallel Host Interface*
• Time of Day
• Up to 47 GPIO
* Each peripheral I/O can be used alternately as a General Purpose I/O if not needed
1.1.4 Energy Information
• Fabricated in high-density CMOS with 3.3V, TTL-compatible digital inputs
• Wait and Stop modes available
1.2 56857 Description
The 56857 is a member of the 56800E core-based family of controllers. It combines, on a single chip, the
processing power of a Digital Signal Processor (DSP) and the functionality of a microcontroller with a
flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,
configuration flexibility, and compact program code, the 56857 is well-suited for many applications. The
56857 includes many peripherals that are especially useful for low-end Internet appliance applications
and low-end client applications such as telephony; portable devices; Internet audio; and point-of-sale
systems, such as noise suppression; ID tag readers; sonic/subsonic detectors; security access devices;
remote metering; sonic alarms.
The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact DSP and
control code. The instruction set is also highly efficient for C Compilers, enabling rapid development of
optimized control applications.
The 56857 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56857 also provides two external
dedicated interrupt lines, and up to 47 General Purpose Input/Output (GPIO) lines, depending on
peripheral configuration.
The 56857 controller includes 40K words of Program RAM, 24K words of Data RAM and 1K of Boot
ROM.
This controller also provides a full set of standard programmable peripherals that include 8-bit parallel
Host Interface, Two Enhanced Synchronous Serial Interfaces (ESSI), one Serial Peripheral Interface (SPI),
two Serial Communications Interfaces (SCI), and one Quad Timer. The ESSIs, SPI, SCIs IO and Quad
Timer can be used as General Purpose Input/Outputs when its primary function is not required.
Freescale Semiconductor
56857 Technical Data, Rev. 6
5
5 Page 
Introduction
Table 3-1 56857 Signal and Package Information for the 100-pin LQFP (Continued)
Pin No. Signal Name
Type
Description
18 VSSA
19 VSSA
55 CS0
VSSA
Analog Ground (VSSA)—This pin supplies an analog ground.
Output
External Chip Select (CS0)—This pin is used as a dedicated GPIO.
GPIOA0
Input/Output
Port A GPIO (0)—This pin is a General Purpose I/O (GPIO) pin when not
configured for host port usage.
56 CS1
Output
External Chip Select (CS1)—This pin is used as a dedicated GPIO.
GPIOA1
Input/Output
Port A GPIO (1)—This pin is a General Purpose I/O (GPIO) pin when not
configured for host port usage.
57 CS2
Output
External Chip Select (CS2)—This pin is used as a dedicated GPIO.
GPIOA2
Input/Output
Port A GPIO (2)—This pin is a General Purpose I/O (GPIO) pin when not
configured for host port usage.
58 CS3
Output
External Chip Select (CS3)—This pin is used as a dedicated GPIO.
GPIOA3
Input/Output
Port A GPIO (3)—This pin is a General Purpose I/O (GPIO) pin when not
configured for host port usage.
22 HD0
Input
Host Address (HD0)—This input provides the address selection for HI
registers.
This pin is disconnected internally.
GPIOB0
Input/Output
Port B GPIO (0)—This pin is a General Purpose I/O (GPIO) pin when not
configured for host port usage.
23 HD1
Input
Host Address (HD1)—This input provides the address selection for HI
registers.
This pin is disconnected internally.
GPIOB1
Input/Output
Port B GPIO (1)—This pin is a General Purpose I/O (GPIO) pins when
not configured for host port usage.
24 HD2
Input
Host Address (HD2)—This input provides the address selection for HI
registers.
This pin is disconnected internally.
GPIOB2
Input/Output
Port B GPIO (2)—This pin is a General Purpose I/O (GPIO) pins when
not configured for host port usage.
Freescale Semiconductor
56857 Technical Data, Rev. 6
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 56857.PDF ] | |
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