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PDF ADP3197 Data sheet ( Hoja de datos )
| Número de pieza | ADP3197 | |
| Descripción | 6-Bit Programmable 2-/3-Phase Synchronous Buck Controller | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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6-Bit Programmable 2-/3-Phase
Synchronous Buck Controller
ADP3197
FEATURES
Selectable 2-phase and 3-phase operation at up to 1 MHz
per phase
±10 mV worst-case differential sensing error over
temperature
Logic-level PWM outputs for interface to external high
power drivers
Enhanced PWM flex mode for excellent load transient
performance
Active current balancing between all output phases
Built-in power good/crowbar blanking that supports
on-the-fly VID code changes
Digitally programmable 0.3750 V to 1.55 V output
Programmable short-circuit protection with
programmable latch-off delay
APPLICATIONS
Desktop PC power supplies for
Next-generation AMD processors
Voltage regulator modules (VRM)
GENERAL DESCRIPTION
The ADP31971is a highly efficient multiphase synchronous buck
switching regulator controller optimized for converting a 12 V
main supply into the core supply voltage required by high perform-
ance, Advanced Micro Devices, AMD processors. It uses an
internal 6-bit digital-to-analog converter (DAC) to read a voltage
identification (VID) code directly from the processor, which is
used to set the output voltage between 0.3750 V and 1.55 V. It uses
a multimode pulse-width modulation (PWM) architecture to
drive the logic level outputs at a programmable switching
frequency that can be optimized for VR size and efficiency.
The phase relationship of the output signals can be programmed
to provide 2-phase or 3-phase operation, allowing for the
construction of up to three complementary buck switching stages.
The ADP3197 supports a programmable slope function to adjust
the output voltage as a function of the load current so it is always
optimally positioned for a system transient. This can be disabled
by connecting the LLSET pin to the CSREF pin.
The ADP3197 also provides accurate and reliable short-circuit
protection, adjustable current limiting, and a delayed power-
good output that accommodates on-the-fly output voltage
changes requested by the CPU.
GND 15
FUNCTIONAL BLOCK DIAGRAM
VCC
24
RT RAMPADJ
9 10
SHUNT
REGULATOR
UVLO
SHUTDOWN
OSCILLATOR
SET EN
16 OD
800mV
EN 1
–
+
CSREF
2.2V
–
+
DAC – 250mV
+
–
PWRGD 2
DELAY
TTSENSE 31
VRHOT 32
THERMAL
THROTTLING
CONTROL
CURRENT
BALANCING
CIRCUIT
+
CMP
–
+
CMP
–
+
–CMP
RESET
RESET
2-/3-PHASE
DRIVER LOGIC
RESET
23 PWM1
22 PWM2
21 PWM3
CROWBAR
CURRENT
LIMIT
20 SW1
19 SW2
18 SW3
ILIMIT 8
DELAY 7
CURRENT
MEASUREMENT
AND LIMIT
14 CSCOMP
+ 12 CSREF
–
13 CSSUM
IREF 17
COMP 5
FBRTN 3
PRECISION
REFERENCE
–
+
+
–
VID DAC
25 26 27 28 29 30
VID5 VID4 VID3 VID2 VID1 VID0
Figure 1.
SOFT START
CONTROL
4 FB
11 LLSET
6 SS
ADP3197
The ADP3197 has a built-in shunt regulator that allows the part
to be connected to the 12 V system supply through a series resistor.
The ADP3197 is specified over the extended commercial tempera-
ture range of 0°C to 85°C and is available in a 32-lead LFCSP.
1Protected by U.S. Patent Number 6,683,441; other patents pending.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
1 page  
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VCC
FBRTN
PWM3, RAMPADJ
SW1 to SW3
<200 ns
All Other Inputs and Outputs
Storage Temperature Range
Operating Ambient Temperature Range
Operating Junction Temperature
Thermal Impedance (θJA)
Lead Temperature
Soldering (10 sec)
Infrared (15 sec)
Rating
−0.3 V to +6 V
−0.3 V to +0.3 V
−0.3 V to VCC + 0.3 V
−5 V to +25 V
−10 V to +25 V
−0.3 V to VCC + 0.3 V
−65°C to +150°C
0°C to 85°C
125°C
100°C/W
300°C
260°C
ADP3197
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages are
referenced to GND.
ESD CAUTION
Rev. 0 | Page 5 of 32
5 Page 
ADP3197
MASTER CLOCK FREQUENCY
The clock frequency of the ADP3197 is set with an external
resistor connected from the RT pin to ground. The frequency
follows the graph in Figure 3. To determine the frequency per
phase, the clock is divided by the number of phases in use. If all
phases are in use, divide by 3. If the PWM3 pin is tied to VCC,
then divide the master clock by 2 for the frequency of the
remaining phases.
OUTPUT VOLTAGE DIFFERENTIAL SENSING
The ADP3197 combines differential sensing with a high accuracy
VID DAC and reference and a low offset error amplifier. This
maintains a worst-case specification of ±10 mV differential
sensing error over its full operating output voltage and temperature
range. The output voltage is sensed between the FB pin and the
FBRTN pin. The FB pin should be connected through a resistor to
the regulation point, usually the remote sense pin of the micro-
processor. The FBRTN pin should be connected directly to the
remote sense ground point. The internal VID DAC and precision
reference are referenced to FBRTN, which has a minimal current
of 65 μA to allow accurate remote sensing. The internal error
amplifier compares the output of the DAC to the FB pin to
regulate the output voltage.
OUTPUT CURRENT SENSING
The ADP3197 provides a dedicated current sense amplifier
(CSA) to monitor the total output current for proper voltage
positioning vs. load current and for current limit detection.
Sensing the load current at the output gives the total average
current being delivered to the load, which is an inherently more
accurate method than peak current detection or sampling the
current across a sense element, such as the low-side MOSFET.
This amplifier can be configured in the following ways,
depending on the objectives of the system:
• Output inductor DCR sensing without a thermistor for
lowest cost
• Output inductor DCR sensing with a thermistor for
improved accuracy with tracking of inductor temperature
• Sense resistors for highest accuracy measurements
The positive input of the CSA is connected to the CSREF pin,
which is connected to the output voltage. The inputs to the
amplifier are summed together through resistors from the
sensing element (such as the switch node side of the output
inductors) to the inverting input, CSSUM. The feedback resistor
between CSCOMP and CSSUM sets the gain of the amplifier,
and a filter capacitor is placed in parallel with this resistor. The
gain of the amplifier is programmable by adjusting the feedback
resistor. If required, an additional resistor divider connected
between CSREF and CSCOMP, with the midpoint connected
to LLSET, can be used to set the load line required by the micro-
processor. The current information is then given as CSREF −
LLSET. This difference signal is used internally to offset the
VID DAC for voltage positioning.
The difference between CSREF and CSCOMP is then used as a
differential input for the current limit comparator. This allows
for the load line to be set independently of the current limit
threshold. In the event that the current limit threshold and load
line are not independent, the resistor divider between CSREF
and CSCOMP can be removed and the CSCOMP pin can be
directly connected to the LLSET pin. To disable voltage posi-
tioning entirely (that is, no load line), connect LLSET to CSREF.
To provide the best accuracy for sensing current, the CSA is
designed to have a low offset input voltage. In addition, the
sensing gain is determined by external resistors so it can be
made extremely accurate.
ACTIVE IMPEDANCE CONTROL MODE
For controlling the dynamic output voltage droop as a function
of output current, a signal proportional to the total output current
at the LLSET pin can be scaled to be equal to the droop impedance
of the regulator times the output current. This droop voltage is
then used to set the input control voltage to the system. The
droop voltage is subtracted from the DAC reference input
voltage directly to tell the error amplifier where the output
voltage should be. This allows enhanced feed-forward response.
CURRENT CONTROL MODE AND THERMAL
BALANCE
The ADP3197 has individual inputs (SW1 to SW3) for each
phase, which are used for monitoring the current in each phase.
This information is combined with an internal ramp to create
a current balancing feedback system that has been optimized
for initial current balance accuracy and dynamic thermal
balancing during operation. This current balance information is
independent of the average output current information used for
positioning, described in the Output Current Sensing section.
The magnitude of the internal ramp can be set to optimize the
transient response of the system. It also monitors the supply
voltage for feed-forward control for changes in the supply. A
resistor connected from the power input voltage to the RAMPADJ
pin determines the slope of the internal PWM ramp. External
resistors can be placed in series with individual phases to create
an intentional current imbalance, if desired, such as when one
phase may have better cooling and can support higher currents.
Resistor RSW1 through Resistor RSW3 can be used for adjusting
thermal balance (see the typical application circuit in Figure 10).
It is best to add these resistors during the initial design, so be
sure that placeholders are provided in the layout.
To increase the current in any given phase, make RSWx for that
phase larger (make RSWx = 0 for the hottest phase and do not change
during balancing). Increasing RSWx to only 500 Ω makes a substan-
tial increase in phase current. Increase each RSWx value by small
amounts to achieve balance, starting with the coolest phase first.
Rev. 0 | Page 11 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADP3197.PDF ] | |
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