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PDF ADG1436 Data sheet ( Hoja de datos )
| Número de pieza | ADG1436 | |
| Descripción | Dual SPDT Switch | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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2Ω Max On Resistance,
±15 V/12 V/±5 V iCMOS™ Dual SPDT Switch
Preliminary Technical Data
ADG1436
FEATURES
2Ω Max On Resistance
0.5Ω Max On Resistance Flatness
200mA continious current
33 V supply range
Fully specified at +12 V, ±15 V, ±5 V
No VL supply required
3 V logic-compatible inputs
Rail-to-rail operation
16-lead TSSOP and 16-lead LFCSP packages
APPLICATIONS
Automatic test equipment
Data aquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Communication systems
Relay Replacement
www.DataSheet4U.com
FUNCTIONAL BLOCK DIAGRAM
ADG1436
S1A
S1B
D1
IN1
IN2
S2A
S2B
D2
SWITCHES SHOWN FOR A LOGIC "1" INPUT
Figure 1.TSSOP package
S1A
D1
S1B
ADG1436
LOGIC
S2A
D2
S2B
GENERAL DESCRIPTION
The ADG1436 is a monolithic CMOS device containing two
independently selectable SPDT switches. An EN input on the
LFCSP package is used to enable or disable the device. When
disabled, all channels are switched off. Each switch conducts
equally well in both directions when on and has an input signal
range that extends to the supplies. In the off condition, signal
levels up to the supplies are blocked. Both switches exhibit
break-before-make switching action for use in multiplexer
applications.
It is designed on an iCMOS process. iCMOS (industrial-
CMOS) is a modular manufacturing process combining high
voltage CMOS (complementary metal-oxide semiconductor)
and bipolar technologies. It enables the development of a wide
range of high performance analog ICs capable of 33 V operation
in a footprint that no previous generation of high voltage parts
has been able to achieve. Unlike analog ICs using conventional
CMOS processes, iCMOS components can tolerate high supply
Rev. PrC
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
IN1 IN2
EN
SWITCHES SHOWN FOR A “1” INPUT LOGIC
Figure 2.LFCSP package
voltages, while providing increased performance, dramatically
lower power consumption, and reduced package size.
The on resistance profile is very flat over the full analog input
range ensuring excellent linearity and low distortion when
switching audio signals. iCMOS construction ensures ultralow
power dissipation, making the part ideally suited for portable
and battery-powered instruments.
PRODUCT HIGHLIGHTS
1. 2Ω Max On Resistance over temperature.
2. Minimum distortion
3. 3 V logic-compatible digital inputs: VIH = 2.0 V, VIL = 0.8 V.
4. No VL logic power supply required.
5. Ultralow power dissipation: <0.03 µW.
6. 16-lead TSSOP and 16-lead 4 mm × 4mm LFCSP
packages.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2007 Analog Devices, Inc. All rights reserved.
1 page  
Preliminary Technical Data
POWER REQUIREMENTS
IDD
IDD
VDD
25°C
0.001
150
1 Guaranteed by design, not subject to production test.
ADG1436
-40°C to
+85°C
-40°C to
+125°C
1.0
300
5/16.5
µA typ
µA max
µA typ
µA max
V
min/max
VDD = 13.2 V
Digital Inputs = 0 V or VDD
Digital Inputs = 5 V
Gnd = 0V, Vss = 0V
DUAL SUPPLY
VDD = 5 V ± 10%, VSS = -5 V ± 10%, GND = 0 V, unless otherwise noted.
Table 3.
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On Resistance Match Between
Channels (∆RON)
25°C
3
0.1
−40°C to
+85°C
4
−40°C to
+125°C
0 V to VDD
On Resistance Flatness (RFLAT(ON))
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINLor IINH
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANS
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
Charge Injection
Off Isolation
0.1
±0.01
±0.5
±0.01
±0.5
±0.04
±1
0.001
3
150
190
85
105
105
125
50
50
50
±2.5
±2.5
±5
130
150
±5
±5
±5
2.0
0.8
±0.5
265
140
170
10
Channel-to-Channel Crosstalk
60
Rev. PrC| Page 5 of 17
Unit Test Conditions/Comments
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = ±3.3V, IS = −10 mA; See figure x
VDD = +4.5 V, VSS = −4.5 V
VS = ±3.3 V , IS = −10 mA
VS = −3 V/0 V/+3 V; IS = −10 mA
VDD = +5.5 V, VSS = −5.5 V
VS = ±4.5 V, VD = ∓4.5 V; See figure x
VS = ±4.5 V, VD = ∓4.5 V; See figure x
VS = VD = ±4.5V; See figure x
V min
V max
µA typ
µA max
pF typ
VIN = VINL or VINH
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
RL = 300 Ω, CL = 35 pF
VS = 3 V; Figure 25
RL = 300 Ω, CL = 35 pF
VS = 3 V; Figure 25
RL = 300 Ω, CL = 35 pF
VS = 3 V; Figure 25
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 3 V; See figure 25
VS = 0 V, RS = 0 Ω, CL = 1 nF; See figure x
RL = 50 Ω, CL = 5 pF, f = 1 MHz; See figure
x
RL = 50 Ω, CL = 5 pF, f = 1 MHz; See figure
x
5 Page 
Preliminary Technical Data
Figure 11. Leakage Current as a Function of VD (VS)
ADG1436
Figure 12. Leakage Currents as a Function of Temperature
Figure 15. Charge Injection vs. Source Voltage
Figure 13. IDD vs. Logic Level
Figure 16. tTRANSITION Times vs. Temperature
Figure 14. Logic Threshold Voltage vs Supply Voltage
Rev. PrC| Page 11 of 17
Figure 17. Off Isolation vs. Frequency
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ADG1436.PDF ] | |
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