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PDF AD9869 Data sheet ( Hoja de datos )
| Número de pieza | AD9869 | |
| Descripción | Broadband Modem Mixed-Signal Front End | |
| Fabricantes | Analog Devices | |
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Broadband Modem Mixed-Signal Front End
AD9869
FEATURES
Low cost 3.3 V CMOS MxFE for broadband modems
12-bit DAC converter
2×/4× interpolation filter
200 MSPS DAC update rate
Integrated 17 dBm line driver with 19.5 dB gain control
12-bit, 80 MSPS, ADC converter
−12 dB to +48 dB low noise RxPGA (<3 nV/√Hz)
Third-order, programmable low-pass filter
Flexible digital data path interface
Half- and full-duplex operation
Pin compatible with the AD9866
Various power-down/reduction modes
Internal clock multiplier (PLL)
2 auxiliary programmable clock outputs
Available in a 64-lead LFCSP_VQ
APPLICATIONS
Broadband wireline networking
GENERAL DESCRIPTION
The AD9869 is a mixed-signal front-end (MxFE®) IC for
transceiver applications requiring Tx path and Rx path
functionality with data rates up to 80 MSPS. A lower cost, pin-
compatible version of the AD9866, the AD9869 removes the
current amplifier (IAMP) IOUTP functionality and limits the
PLL VCO operating range of 80 MHz to 200 MHz.
The part is well suited for half- and full-duplex applications.
The digital interface is extremely flexible, allowing simple
interfacing to digital back ends that support half- or full-duplex
data transfers, often allowing the AD9869 to replace discrete
ADC and DAC solutions. Power-saving modes include the
ability to reduce power consumption of individual functional
blocks or power down unused blocks in half-duplex applications.
A serial port interface (SPI) allows software programming of
the various functional blocks. An on-chip PLL clock multiplier
and synthesizer provide all the required internal clocks, as well
as two external clocks, from a single crystal or clock source.
The Tx signal path consists of a 2×/4× low-pass interpolation
filter, a 12-bit TxDAC, and a line driver. The transmit path
signal bandwidth can be as high as 34 MHz at an input data rate
FUNCTIONAL BLOCK DIAGRAM
PWRDWN
MODE
TXEN/TXSYNC
TXCLK/TXQUIET
ADIO[11:6]/
Tx[5:0]
ADIO[5:0]/
Rx[5:0]
AD9869
2-4X
12
TxDAC
IAMP
0 TO –7.5dB 0 TO –12dB
CLK
SYNC.
2M CLK
MULTIPLIER
IOUTN+
IOUTN–
CLKOUT1
CLKOUT2
OSCIN
XTAL
RXEN/RXSYNC
RXCLK
AGC[5:0]
PORT
SPI
PORT
12
ADC
80MSPS
2-POLE
LPF
1-POLE
LPF
6
0 TO 6dB –6 TO +18dB –6 TO +24dB
4 REGISTER ∆ = 1dB ∆ = 6dB
∆ = 6dB
CONTROL
Figure 1.
RX+
RX–
of 80 MSPS. The TxDAC provides differential current outputs
that can be steered directly to an external load or to an internal
low distortion current amplifier (IAMP) capable of delivering
17 dBm peak signal power. Tx power can be digitally controlled
over a 19.5 dB range in 0.5 dB steps.
The receive path consists of a programmable amplifier (RxPGA),
a tunable low-pass filter (LPF), and a 12-bit ADC. The low noise
RxPGA has a programmable gain range of −12 dB to +48 dB in
1 dB steps. Its input referred noise is less than 3 nV/√Hz for gain
settings beyond 36 dB. The receive path LPF cutoff frequency
can be set over a 15 MHz to 35 MHz range or it can be simply
bypassed. The 12-bit ADC achieves excellent dynamic performance
up to an 80 MSPS span. Both the RxPGA and the ADC offer
scalable power consumption allowing power/performance
optimization.
The AD9869 provides a highly integrated solution for many
broadband modems. It is available in a space-saving package, a
16-lead LFCSP, and is specified over the commercial temperature
range (−40°C to +85°C).
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2011 Analog Devices, Inc. All rights reserved.
1 page  
AD9869
Parameter
PLL CLK MULTIPLIER
OSCIN Frequency Range
PLL M Factor Set to 2
PLL M Factor Set to 4
PLL M Factor Set to 8
Internal VCO Frequency Range
Duty Cycle
OSCIN Impedance
CLKOUT1 Jitter6
CLKOUT2 Jitter7
CLKOUT1 and CLKOUT2 Duty Cycle8
Temp Test Level1 Min Typ
Max Unit
Full IV
Full IV
Full IV
Full IV
Full II
25°C V
25°C III
25°C III
Full III
40 80
20 50
10 25
80 200
40 60
10||03
12
6
45
55
MHz
MHz
MHz
MHz
%
ΜΩ||pF
ps rms
ps rms
%
1 See the Explanation of Test Levels section.
2 Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1.23 V external reference and a 1 V p-p differential analog input).
3 TxDAC IOUTP_FS = 20 mA, differential output with 1:1 transformer with source and load termination of 50 Ω, fOUT = 5 MHz, 4x interpolation.
4 IOUTN full-scale current = 80 mA, fOSCIN = 80 MHz, fDAC =160 MHz, 2x interpolation.
5 Use external amplifier to drive additional load.
6 Internal VCO operates at 200 MHz; set to divide-by-1.
7 Because CLKOUT2 is a divided-down version of OSCIN, its jitter is typically equal to OSCIN.
8 CLKOUT2 is an inverted replica of OSCIN, if set to divide-by-1.
Rx PATH SPECIFICATIONS
AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, half- or full-duplex operation with CONFIG = 0 default power bias settings,
unless otherwise noted.
Table 2.
Parameter
Rx INPUT CHARACTERISTICS
Input Voltage Span
RxPGA Gain = −10 dB
RxPGA Gain = +48 dB
Input Common-Mode Voltage
Differential Input Impedance
Input Bandwidth with RxLPF Disabled, RxPGA = 0 dB
Input Voltage Noise Density
RxPGA Gain = 36 dB, f−3 dBF = 26 MHz
RxPGA Gain = 48 dB, f−3 dBF = 26 MHz
RxPGA CHARACTERISTICS
Minimum Gain
Maximum Gain
Gain Step Size
Gain Step Accuracy
Gain Range Error
RxLPF CHARACTERISTICS
Cutoff Frequency (f−3 dBF ) Range
Attenuation at 55.2 MHz with f−3 dBF = 21 MHz
Pass-Band Ripple
Settling Time
5 dB RxPGA Gain Step @ fADC = 50 MSPS
60 dB RxPGA Gain Step @ fADC = 50 MSPS
ADC DC CHARACTERISTICS
Resolution
Conversion Rate
Temp Test Level1 Min Typ
Max Unit
Full III
Full III
25°C III
25°C III
25°C III
25°C III
25°C III
25°C III
25°C III
25°C III
25°C III
25°C III
Full III
25°C III
25°C III
25°C III
25°C III
N/A N/A
Full II
6.33
8
1.3
400||4.0
53
2.7
2.4
−12
48
1
Monotonic
0.5
15
20
±1
35
20
100
12
20
80
V p-p
mV p-p
V
Ω||pF
MHz
nV/√Hz
nV/√Hz
dB
dB
dB
dB
dB
MHz
dB
dB
ns
ns
Bits
MSPS
Rev. A | Page 4 of 36
5 Page 
AD9869
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADIO11/Tx[5] 1
ADIO10/Tx[4] 2
ADIO9/Tx[3] 3
ADIO8/Tx[2] 4
ADIO7/Tx[1] 5
ADIO6/Tx[0] 6
ADIO5/Rx[5] 7
ADIO4/Rx[4] 8
ADIO3/Rx[3] 9
ADIO2/Rx[2] 10
ADIO1/Rx[1] 11
ADIO0/Rx[0] 12
RXEN/RXSYNC 13
TXEN/TXSYNC 14
TXCLK/TXQUIET 15
RXCLK 16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PIN 1
IDENTIFIER
AD9869
TOP VIEW
(Not to Scale)
48 AVSS
47 AVSS
46 IOUTN–
45 NC
44 AVSS
43 AVDD
42 REFIO
41 REFADJ
40 AVDD
39 AVSS
38 RX+
37 RX–
36 AVSS
35 AVDD
34 AVSS
33 REFT
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NOTES
1. THE EXPOSED PAD MUST BE SOLDERED TO GND.
Figure 2. Pin Configuration
Table 9. Pin Function Descriptions
Pin No.
Mnemonic
1 ADIO11
Tx[5]
2 to 5
ADIO10 to ADIO7
Tx[4:1]
6 ADIO6
Tx[0]
7 ADIO5
Rx[5]
8, 9 ADIO4, ADIO3
Rx[4:3]
10 ADIO2
Rx[2]
11 ADIO1
Rx[1]
12 ADIO0
Rx[0]
13 RXEN
RXSYNC
14 TXEN
TXSYNC
Mode1
HD
FD
HD
FD
HD
FD
HD
FD
HD
FD
HD
FD
HD
FD
HD
FD
HD
FD
HD
FD
Description
MSB of ADIO Buffer.
MSB of Tx Nibble Input.
Bit 10 to Bit 7 of ADIO Buffer.
Bit 4 to Bit 1 of Tx Nibble Input.
Bit 6 of ADIO Buffer.
LSB of Tx Nibble Input.
Bit 5 of ADIO Buffer.
MSB of Rx Nibble Output.
Bit 4 to Bit 3 of ADIO Buffer.
Bit 4 to Bit 3 of Rx Nibble Output.
Bit 2 of ADIO Buffer.
Bit 2 of Rx Nibble Output.
Bit 1 of ADIO Buffer.
Bit 1 of Rx Nibble Output.
LSB of ADIO Buffer.
LSB of Rx Nibble Output.
ADIO Buffer Control Input.
Rx Data Synchronization Output.
Tx Path Enable Input.
Tx Data Synchronization Input.
Rev. A | Page 10 of 36
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9869.PDF ] | |
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