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PDF HYB39S256400CTL Data sheet ( Hoja de datos )
| Número de pieza | HYB39S256400CTL | |
| Descripción | (HYB39S256xxxCT) 256 MBit Synchronous DRAM | |
| Fabricantes | Infineon Technologies | |
| Logotipo |  |
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256 MBit Synchronous DRAM
HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
• High Performance:
-7.5 -8 Units
fCK 133 125 MHz
tCK3 7.5
8
ns
tAC3 5.4
6
ns
tCK2 10 10
ns
tAC2 6 6 ns
• Fully Synchronous to Positive Clock Edge
• 0 to 70 °C operating temperature
• Four Banks controlled by BA0 & BA1
• Programmable CAS Latency: 2 & 3
• Programmable Wrap Sequence: Sequential
or Interleave
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• Programmable Burst Length:
1, 2, 4, 8
• Full page burst length for
sequential wrap around
• Multiple Burst Read with Single Write
Operation
• Automatic and Controlled Precharge
Command
• Data Mask for Read / Write control (x4, x8)
• Data Mask for byte control (x16)
• Auto Refresh (CBR) and Self Refresh
• Power Down and Clock Suspend Mode
• 8192 refresh cycles / 64 ms (7,8 µs)
• Random Column Address every CLK
( 1-N Rule)
• Single 3.3V +/- 0.3V Power Supply
• LVTTL Interface versions
• Plastic Packages:
P-TSOPII-54 400mil width (x4, x8, x16)
• -7.5 parts for PC133 3-3-3 operation
-8 parts for PC100 2-2-2 operation
The HYB39S256400/800/160CT(L) are four bank Synchronous DRAM’s organized as 4 banks x
16MBit x4, 4 banks x 8MBit x8 and 4 banks x 4Mbit x16 respectively. These synchronous devices
achieve high speed data transfer rates for CAS-latencies by employing a chip architecture that
prefetches multiple bits and then synchronizes the output data to a system clock. The chip is
fabricated with INFINEON’s advanced 0.17 µm 256MBit DRAM process technology.
The device is designed to comply with all industry standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is
possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single
3.3V +/- 0.3V power supply and are available in TSOPII packages.
INFINEON Technologies
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HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
Column Address
Counter
Column Addresses
A0 - A9, AP,
BA0, BA1
Column Address
Buffer
Row Addresses
A0 - A12,
BA0, BA1
Row Address
Buffer
Refresh Counter
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Row
Decoder
Memory
Array
Bank 0
8192
x 1024
x 8 Bit
Row
Decoder
Memory
Array
Bank 1
8192
x 1024
x 8 Bit
Row
Decoder
Memory
Array
Bank 2
8192
x 1024
x 8 Bit
Row
Decoder
Memory
Array
Bank 3
8192
x 1024
x 8 Bit
Input Buffer Output Buffer
DQ0 - DQ7
Block Diagram for 32M x 8 SDRAM ( 13 / 10 / 2 addressing)
Control Logic &
Timing Generator
SPB04128
INFINEON Technologies
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HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
Power On and Initialization
The default power on state of the mode register is supplier specific and may be undefined.
The following power on and initialization sequence guarantees the device is preconditioned to each
users specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and
initialized in a predefined manner.During power on, all VDD and VDDQ pins must be built up
simultaneously to the specified voltage when the input signals are held in the “NOP” state. The
power on voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies. The CLK
signal must be started at the same time. After power on, an initial pause of 200 µs is required
followed by a precharge of all banks using the precharge command. To prevent data contention on
the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial
pause period. Once all banks have been precharged, the Mode Register Set Command must be
issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also
required.These may be done before or after programming the Mode Register. Failure to follow these
steps may lead to unpredictable start-up modes.
Programming the Mode Register
The Mode register designates the operation mode at the read or write cycle. This register is
divided into 4 fields. A Burst Length Field to set the length of the burst, an Addressing Selection bit
to program the column access sequence in a burst cycle (interleaved or sequential), a CAS Latency
Field to set the access time at clock cycle and a Operation mode field to differentiate between
normal operation (Burst read and burst Write) and a special Burst Read and Single Write mode.
www.DataSheet4AU.fctoemr the initial power up, the mode set operation must be done before any activate command . Any
content of the mode register can be altered by re-executing the mode set command. All banks must
be in precharged state and CKE must be high at least one clock before the mode set operation. After
the mode register is set, a Standby or NOP command is required. Low signals of RAS, CAS, and
WE at the positive edge of the clock activate the mode set operation. Address input data at this
timing defines parameters to be set as shown in the previous table.
Read and Write Operation
When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle
starts. According to address data, a word line of the selected bank is activated and all of sense
amplifiers associated to the wordline are set. A CAS cycle is triggered by setting RAS high and CAS
low at a clock timing after a necessary delay, tRCD, from the RAS timing. WE is used to define either
a read (WE = H) or a write (WE = L) at this stage.
SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read
or write operations are allowed at up to a 133 MHz data rate. The numbers of serial data bits are the
burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page. Column
addresses are segmented by the burst length and serial data accesses are done within this
boundary. The first column address to be accessed is supplied at the CAS timing and the
subsequent addresses are generated automatically by the programmed burst length and its
sequence. For example, in a burst length of 8 with interleave sequence, if the first address is ‘2’,
then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5.
Full page burst operation is only possible using sequential burst type and page length is a function
of the I/O organisation and column addressing. Full page burst operation does not self terminate
INFINEON Technologies
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11 Page | ||
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